Static information storage and retrieval – Floating gate – Disturbance control
Reexamination Certificate
1999-05-28
2001-03-13
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Disturbance control
C365S145000, C365S192000, C365S065000, C365S194000
Reexamination Certificate
active
06201731
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention in general relates to destructive readout electronic memories, in particular ferroelectric memories, and more particularly to such a memory in which the data cannot be disturbed during power-up, power-down, brownouts and other sub-unstable electronic conditions.
2. Statement of the Problem
Ferroelectric memories are becoming commercially important because they are nonvolatile, can be made at relatively low cost, and can be written to and read at voltages and speeds typical of conventional DRAM and SRAM computer memories; that is, at voltages of from 1 to 5 volts in times of the order of 10 to 100 nanoseconds. See, for example, Orlando Auciello, James F. Scott, and Ramanmoorthy Ramesh, “The Physics of Ferroelectric Memories”,
Physics Today,
Vol. 51, No. Jul. 7, 1998, pp. 22-27. However, these advantages also lead to problems with the memories as compared to other nonvolatile memories. Conventional nonvolatile memories, such as EPROMs, can be written to only by applying relatively high voltages, i.e. 15 volts, for relatively long periods, i.e. 100 microseconds to 200 microseconds. Thus, once they are programmed, the data of EPROMs and other non-ferroelectric nonvolatile memories cannot be disturbed by voltages at which conventional computers operate. However, since ferroelectric memories can be rewritten by relatively short, relatively low voltage pulses, stray voltages, such as can occur during power-up, power-down, and other non-optimal electronic conditions can cause the loss of data.
Most nonvolatile memories, such as EPROMs, EEPROMs, and flash memories, are non-destructive readout memories. In destructive readout volatile memories, such as DRAM, it does not matter whether the data is disturbed on power-up or power-down because, due to their volatility, the systems they are used in expect that data will be lost on power-down.
Present commercial ferroelectric memories utilize a ferroelectric capacitor as the storage medium and an electric field must be placed across the storage capacitor to read it. This reading electric field can alter the state of the memory cell. Thus, ferroelectric memories are destructive read-out memories. See, for example, the memories described in U.S. Pat. No. 5,029,128 issued Jul. 2, 1991 to Haruki Toda, and U.S. Pat. No. 5,406,510 issued Apr. 11, 1995 to Takashi Mihara et. al. Such destructive read-out memories include a rewrite function in which the data read out is restored to the memory cell immediately after it is read. The rewrite function takes time, and if the memory function is truncated, such as by a power loss, while or immediately after a cell is read and before the rewrite cycle can be completed, the data for that cell will be lost. Such data loss is not acceptable for nonvolatile memories. Most commercial memories include power-off and power-on reset functions. The power-off function shuts the system down when the power drops to or below a predetermined voltage, which voltage we shall refer to as the “OFF threshold” voltage. The power-on-reset function resets latches and other resettable circuits when the power rises to or above a predetermined voltage, which voltage we shall refer to as the “ON threshold” voltage. A brownout is an electrical occurrence in which the power drops below the OFF threshold voltage and then immediately comes back up to the ON threshold voltage. If a brownout occurs just as a memory cell is being read and is very short, the power-on-reset function can occur before the rewrite function is finished. In this case, the latches or other multiple state devices that are holding the data to be rewritten can be reset before the data is rewritten. If this occurs, data will be lost. Similarly, data can be lost in other instances when a destructive read-out electronic memory is reset or addressed due to some other non-optimum condition while a memory cell is being read or being rewritten. Brownouts and other unstable conditions that can result in the loss of data occur frequently in certain types of ferroelectric memories. For instance, one important application of ferroelectric memories is in contactless radio frequency identification (RFID) cards. If such an RFID card is being held in a fringe reception area, a number of brownout conditions can occur in a short time leading to loss of significant data.
For the above reasons, it would be highly desirable to have a ferroelectric, destructive read-out electronic memory such that sub-optimum electronic conditions, such as occur on power-up, power-down, and brownouts, cannot cause a loss of data.
3. Solution to the Problem
The present invention solves the above problem by providing a disturb prevention circuit and method that prevents unstable power conditions from disturbing data in the memory cells of a memory system.
In one embodiment, the disturb prevention circuit holds conducting lines in the memory to predetermined voltage states during power-up, power-down, brownouts, and other non-optimal electronic conditions. These predetermined voltage states are such that the probability of data being disturbed at these times is significantly reduced. Preferably, the disturb prevention circuit holds the conducting lines that can carry voltages that can disturb the memory cell at the same voltage, preferably ground, during power-up and power-down.
In another embodiment of the invention, the disturb prevention circuit comprises a delay circuit that delays application of power to the memory array until the control logic is powered up.
In a further embodiment of the invention, the disturb prevention circuit disables a control signal to the memory until the control logic is in a stable electronic state.
In still another embodiment, for a time sufficient to complete the rewrite function, the disturb prevention circuit pauses the logic circuitry that applies signals to the memory array.
In yet another embodiment, a data element holding the data to be rewritten to the memory is frozen for a time sufficient to complete the rewrite function.
The invention provides a destructive readout, nonvolatile memory system comprising: a power source for applying electrical power to the memory system; a destructive readout, nonvolatile memory cell for holding data; and a disturb prevention circuit for preventing the data from being disturbed during a period when the electrical power is unstable.
The invention also provides a ferroelectric memory system comprising: a power source for applying electrical power to the memory system; a memory cell for holding data, the memory cell including a ferroelectric material; and a disturb prevention circuit for preventing the data from being disturbed during a period when the electrical power is unstable. Preferably, the period is selected from the group consisting of a power-up period, a power-down period, and a brownout period. Preferably, the disturb prevention circuit comprises a circuit for preventing disturb voltages from being applied to the memory cell during the period. Preferably, the memory includes: a circuit for reading the data and rewriting the data to the memory cell after it has been read; and the disturb prevention circuit comprises a circuit for preventing loss of the data before it is rewritten. Preferably, the memory includes a conductor directly electrically connected to or directly electrically connectable to the memory cell, and the disturb prevention circuit comprises a clamping circuit for clamping the conductor to a predetermined voltage. Preferably, there are two of the conductors, the two of the conductors comprise a bit line and a word line, and the disturb prevention circuit comprises a circuit for clamping the word line and the bit line to the predetermined voltage. Preferably, the voltage is the memory system ground. Preferably, the memory cell is part of an array of memory cells, the memory system further includes a logic circuit for applying signals to the array of memory cells and a power supply for applying power to the logic circuit and the memory array,
Coombe George B.
Derbenwick Gary F.
Kamp David A.
Meester Troy A.
Celis Semiconductor Corporation
Duft, Graziano & Forest, P.C.
Nelms David
Yoha Connie C.
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