Electronic memory testing device

Details Electronic memory testing device Electronic memory testing device

1989-11-06

1991-06-25

Baker, Stephen M.

Excavating

371212, G01R 3128

Patent

active

050273540

ABSTRACT:
A verification circuit comprising a CPU, a RAM connected with the CPU and a data A is written therein, an I/O port connected at input thereof an output of said CPU and an output of the RAM for receiving the data A from the RAM, a plurality of drivers each connected with the output of the RAM via said I/O port, the drivers being turned on while a control signal is "1" and turned off while the control signal is "0", a PROM connected with an output of the driver, the data A written in said PROM when the control signal is "1", and a data B to be compared with the data A is read from the PROM when the control signal is "0", a reference voltage having H and L levels, a plurality of analog switches each issuing H level of the reference voltage while the data A is "1" and L level of the reference voltage while the data A is "0", and a plurality of comparators each having one input terminal connected with an output of the analog switch and the other input terminal connected with the output of the PROM. The verification circuit may further include a plurality of the exclusive OR circuit and a gate.

REFERENCES:
patent: 3622876 (1971-11-01), Ure et al.
patent: 4412327 (1983-10-01), Fox et al.
patent: 4517661 (1985-05-01), Graf et al.
patent: 4656632 (1987-04-01), Jackson
patent: 4696005 (1987-09-01), Millham et al.

Affiliated with

Also associated with

Rating

Electronic memory testing device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Electronic memory testing device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electronic memory testing device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1046100