Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
1999-11-19
2003-01-14
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S759000, C257S040000, C257S700000
Reexamination Certificate
active
06507113
ABSTRACT:
BACKGROUND
The invention relates generally to electrical interconnections and more particularly to electronic interface structure fabrication methods.
Ball grid array (BGA) technology provides a high density of interconnections per unit area, but mismatches of coefficients of thermal expansion (CTEs) occur when ceramic or polymer BGA substrates and printed circuit boards are joined and often result in cracked solder joints, especially as the size of the substrates and temperature ranges are increased. In column grid array (CGA) techniques and other BGA techniques, a eutectic solder is applied to printed circuit board and multi-chip module array pads and the resulting joint is soldered to a higher temperature solder column or ball which does not melt. Both BGA and CGA structures can be inflexible and vulnerable to damage. For various types of BGA and CGA, increases in reliability are attempted by elaborate under-filling of the structures with polymer glues to reinforce the interfaces and reduce the effects of the CTE mismatch on the solder joints. The polymer glues, however, impair repairability because of the difficulty in removing the glues after hardening. Furthermore, these types of structures require two separate solder steps, are more expensive than conventional solder structures, and require more vertical space due to increased height of the joints.
One conventional micro ball grid array interface technique for attaching a semiconductor circuit chip directly to a substrate is to use a series of solder bumps clustered at the center of the chip to constrain the area over which stresses between differing coefficients of thermal expansion occur. In this embodiment, chips have their pads reconfigured and solder micro bumps are applied over the reconfigured pads. In one embodiment, ball grid array processes are used with the temperature range being constrained during device operation to 30° C. to 70° C. in an effort to avoid CTE stress effects. In another ball grid array interface technique, the area where the chip faces the printed circuit board or substrate is not used for direct interconnection. Instead, metallization is routed from the chip to adjacent support structures which then have solder ball connections. This technique can create size and pin count limitations as well as electrical parasitic effects.
Commonly assigned Wojnarowski et al., U.S. Pat. No. 5,900,674, describes an interface including a surface having an electrically conductive pad; a compliant coating over the surface having a via extending to the pad; metallization patterned over the compliant coating and extending into the via; a low modulus dielectric interface layer overlying the compliant coating and having an interface via extending to the metallization; and a floating pad structure including floating pad metallization patterned over the dielectric interface layer with a first portion forming a central pad and a second portion forming an extension from the central pad extending into the interface via. The “floating pad” structure is used to increase reliability by providing stress and thermal accommodation of the two materials and permitting movement of the floating pad independent of the base pad. The extension provides stress relief for different coefficients of thermal expansion. The floating pad interface structures can include a single pad and extension or several extensions in situations wherein a single extension is not sufficient for extreme thermal stress/strain situations. The resulting structure accommodates thermal and material stresses without submitting the via interconnect areas to forces that can crack vias or break connections at the pads. The floating pads permit movement independent of a base surface underlying the pads while providing electrical interconnections through selected materials that are specifically patterned to provide low forces at the via areas and thus accommodate differential thermal stresses which may be caused by large CTE differences.
Commonly assigned Wojnarowski et al., U.S. Pat. No. 5938,452 describes a more flexible interface structure for electronic devices that does not require an underlying base surface and that can be used for relieving stress from structures such as multi-chip modules (MCMs), wafers, individual dies or chips, microelectromechanical structures (MEMs), printed circuit boards, and surface mount technologies which may be caused from coefficient of thermal expansion mismatches with connections such as those formed by ball grid arrays, micro ball grid arrays, column grid arrays, flip chips, solder joints, or tape automated bonding connections. In one embodiment, a film interface includes a film; flexible material attached to a portion of the film; and surface metallization on the flexible material. The film has at least one via extending therethrough to the surface metallization. A floating pad structure including floating pad metallization patterned over the flexible material and the surface metallization has a first portion forming a central pad and a second portion forming at least one extension from the central pad and extending into the at least one via.
The floating pad embodiments of aforementioned U.S. Pat. Nos. 5,900,674 and 5,938,452 can extend solder attach life by a factor of about ten. However, the fabrication sequences involve complex deposition and via formation processes and are therefore expensive.
SUMMARY
It would therefore be desirable to have an electronic interface structure with a simplified fabrication sequence as compared with fabrication sequences of present electronic interface structures.
In accordance with one embodiment of the present invention, an electronic interface structure includes a base; at least one elastomeric island supported by the base; and patterned metallization overlying the at least one elastomeric island and including at least one floating pad at least partially overlying the at least one elastomeric island.
In accordance with another embodiment of the present invention, an electronic interface structure includes a base; a first dielectric layer overlying the base and having at least one first dielectric layer opening therein; a second dielectric layer overlying the first dielectric layer; and patterned metallization overlying the second dielectric layer and including at least one floating pad at least partially overlying the at least one opening.
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J. Fjelstad, “Wafer Level Packaging of Compliant CSPs Using Flexible Film Interposers”, HDI Magazine, Spring 1999, 6 pages.
Fillion Raymond Albert
Kolc Ronald Frank
Wojnarowski Robert John
Agosti Ann M.
Breedlove Jill M.
Chu Chris C.
Lee Eddie
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