Patent
1989-12-14
1992-05-05
LaRoche, Eugene R.
357 236, 357 238, 357 235, H01L 2910
Patent
active
051112574
ABSTRACT:
A non-volatile semiconductor memory device includes a substrate (1) having a plurality of element-forming regions (3), a plurality of recesses (32) located between the element-forming regions (3), and a plurality of element-isolating regions (31); word lines (8a to 8d); bit lines (10) orthogonal to this word lines; and memory cells (511) each formed at the point of intersection of these word and bit lines at each element-forming region (3). Each memory cell (511) includes an electrically floating electrode (5) in the form of a flat plate, a control gate electrode (7) in the form of a substantially flat plate formed on the floating gate electrode (5) and connected to the word lines (8a to 8d), and a pair of impurity regions (21, 23) formed respectively at opposite sides of the floating gate electrode (5) on the surface of a semiconductor substrate (1). An element-isolating region (31) includes an element-isolating electrode layer (30) formed on the surface of the semiconductor substrate (1) and in the recesses (32).
REFERENCES:
patent: 4855804 (1989-08-01), Borgami et al.
patent: 4900693 (1990-02-01), Manning
M. Van Buskirk et al., "E-PROMs Graduate to 256-K Density With Scaled n-channel Process", Intel Corporation Technical article Electronics, published Feb. 24, 1983.
Andoh Nobuaki
Ueda Osamu
LaRoche Eugene R.
Mitsubishi Denki & Kabushiki Kaisha
Ratliff R.
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