Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Patent
1998-03-06
2000-10-31
Zweizig, Jeffrey
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
326 56, H03K 300
Patent
active
061408484
DESCRIPTION:
BRIEF SUMMARY
FIELD OF USE
This invention relates to electronic circuits. In particular, this invention relates to reducing power consumption in electronic circuits and conditioning signals in electronic circuits.
BACKGROUND ART
An electronic circuit consumes power in various ways. For example, power is consumed when input signals to elements of the circuit change state. The power consumption occurs as the result of the charging and discharging of parasitic capacitances associated with the inputs to the circuit elements and with electrical conductors that provide the input signals to circuit elements. Power dissipation does not occur in the parasitic capacitance associated with a signal, but in the output resistance of the driver circuit which is the source of the signal.
A large portion of the power consumption in a modern integrated circuit ("IC") occurs in the signal drivers which drive the output pins of the IC and thus also the inputs to any other circuits or ICs connected to the output pins, typically by way of electrically conductive tracks formed on a printed wiring board ("PWB"). The parasitic capacitance associated with (i.e., driven by) each output signal driver is typically much higher than that associated with the internal signals within the IC. Consequently, the power dissipation is high.
A further problem associated with the output drivers of an IC results from the fact that the associated wiring, both within the IC package and on the PWB, is relatively long and therefore has high inductance. This inductance commonly causes undesirable signal characteristics such as "ringing" and "overshoot".
Referring to the drawings, FIG. 1a illustrates a conventional CMOS inverting output driver 10 formed as part of an IC. Output driver 10 generates an inverted driver output voltage signal V.sub.DO in response to a driver input voltage signal V.sub.I. Driver 10 is connected through electrical conductor 12 of a PWB to load circuitry 14. Specifically, electrical conductor 12 converts driver output voltage V.sub.DO into a conductor output voltage signal V.sub.BO that drives a group of digital CMOS ICs 16 in load 14.
Driver circuit 10 is formed with N-channel insulated-gate field-effect transistor ("FET") QA and P-channel insulated-gate FET QB whose gate electrodes receive driver input voltage V.sub.I. The sources of FET QA and QB are respectively connected to a source of a low supply voltage V.sub.SS, typically ground reference (0 volt), and a source of a high supply voltage V.sub.DD. The QA and QB drains are connected together to provide driver output voltage V.sub.DO.
N-channel FET QA is turned on by raising input voltage V.sub.I to a suitably high level. On the other hand, FET QB is turned on by reducing voltage V.sub.I to a suitably low level. Accordingly, only one of FETs QA and QB is conductive during steady-state operation. If input voltage V.sub.I is high, FET QA is turned on to pull output voltage V.sub.DO to a low value close to V.sub.SS. Conversely, output voltage V.sub.DO is at a high value close to V.sub.DD when input voltage V.sub.I is low and causes FET QB to be turned on.
The "on" resistance of each of FETs QA and QB is normally quite low. Consequently, output voltage V.sub.DO makes a rapid transition from V.sub.SS to V.sub.DD when input voltage V.sub.I makes a high-to-low transition. Likewise, output voltage V.sub.DD makes a rapid transition from V.sub.DD to V.sub.SS when input voltage makes a low-to-high transition. During a transition, there is typically a brief period when both of FETs QA and QB are conductive.
PWB electrical conductor 12, commonly referred to as an interconnect, consists of a length of copper track and a ground plane at the V.sub.SS potential. The steps shown in the line passing through conductor 12 in FIG. 1a qualitatively represent the changes in direction that conductor 12 makes on the PWB. The ground plane is represented by the block in slanted shading. CMOS ICs 16 in load 14 are also variously connected to the V.sub.SS supply.
FIG. 1a does not explicitly show the various para
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patent: 5036222 (1991-07-01), Davis
patent: 5373199 (1994-12-01), Shichinohe et al.
patent: 5734285 (1998-03-01), Harvey
Wyatt, "Reactive CCD drive saves power", EDN, Jan. 19, 1989, pp. 206-211.
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