Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2000-02-04
2001-03-13
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S112000
Reexamination Certificate
active
06201420
ABSTRACT:
BACKGROUND ART
An electronic circuit consumes power in various ways. For example, power is consumed when input signals to elements of the circuit change state. The power consumption occurs as the result of the charging and discharging of parasitic capacitances associated with the inputs to the circuit elements and with electrical conductors that provide the input signals to circuit elements. Power dissipation does not occur in the parasitic capacitance associated with a signal, but in the output resistance of the driver circuit which is the source of the signal.
A large portion of the power consumption in a modern integrated circuit (“IC”) occurs in the signal drivers which drive the output pins of the IC and thus also the inputs to any other circuits or ICs connected to the output pins, typically by way of electrically conductive tracks formed on a printed wiring board (“PWB”). The parasitic capacitance associated with (i.e., driven by) each output signal driver is typically much higher than that associated with the internal signals within the IC. Consequently, the power dissipation is high.
A further problem associated with the output drivers of an IC results from the fact that the associated wiring, both within the IC package and on the PWB, is relatively long and therefore has high inductance. This inductance commonly causes undesirable signal characteristics such as “ringing” and “overshoot”.
Referring to the drawings,
FIG. 1
a
illustrates a conventional CMOS inverting output driver
10
formed as part of an IC. Output driver
10
generates an inverted driver output voltage signal V
DO
in response to a driver input voltage signal V
I
. Driver
10
is connected through electrical conductor
12
of a PWB to load circuitry
14
. Specifically, electrical conductor
12
converts driver output voltage V
DO
) into a conductor output voltage signal V
BO
that drives a group of digital CMOS ICs
16
in load
14
.
Driver circuit
10
is formed with N-channel insulated-gate field-effect transistor (“FET”) QA and P-channel insulated-gate FET QB whose gate electrodes receive driver input voltage V
I
. The sources of FET QA and QB are respectively connected to a source of a low supply voltage V
SS
, typically ground reference (0 volt), and a source of a high supply voltage V
DD
. The QA and QB drains are connected together to provide driver output voltage V
DO
.
N-channel FET QA is turned on by raising input voltage V
I
to a suitably high level. On the other hand, FET QB is turned on by reducing voltage V
I
to a suitably low level. Accordingly, only one of FETs QA and QB is conductive during steady-state operation. If input voltage V
I
is high, FET QA is turned on to pull output voltage V
DO
to a low value close to V
SS
. Conversely, output voltage V
DO
is at a high value close to V
DD
when input voltage V
I
is low and causes FET QB to be turned on.
The “on” resistance of each of FETs QA and QB is normally quite low. Consequently, output voltage V
DO
makes a rapid transition from V
SS
to V
DD
when input voltage V
I
makes a high-to-low transition. Likewise, output voltage V
DD
makes a rapid transition from V
DD
to V
SS
when input voltage makes a low-to-high transition. During a transition, there is typically a brief period when both of FETs QA and QB are conductive.
PWB electrical conductor
12
, commonly referred to as an interconnect, consists of a length of copper track and a ground plane at the V
SS
potential. The steps shown in the line passing through conductor
12
in
FIG. 1
a
qualitatively represent the changes in direction that conductor
12
makes on the PWB. The ground plane is represented by the block in slanted shading. CMOS ICs
16
in load
14
are also variously connected to the V
SS
supply.
FIG. 1
a
does not explicitly show the various parasitic circuit elements which typically exist in any such circuit arrangement. For example, PWB conductor
12
is typically inductive and is also coupled to the nearby ground plane by parasitic capacitance. When driver
10
is formed as part of an IC within an IC package, the conductors internal to the package introduce further parasitic inductance and capacitance. Likewise, when ICs
16
are contained within IC packages, ICs
16
introduce further parasitic inductance and capacitance.
FIG. 1
b
shows a simplified electrical model of the circuitry in
FIG. 1
a
. Inverting driver
10
is modeled by a switch SW in series with an output resistor R
ON
. Switch SW is controlled by input voltage V
I
. Resistor R
ON
represents the source-drain resistance of each FET QA or QB when it is turned on. PWB conductor
12
is modeled by parasitic inductance LB with distributed parasitic capacitance CB. Inductance LB and capacitance CB also model the parasitic inductance and capacitance of conductors internal to IC packages when driver
10
is formed as part of an IC contained in an IC package and/or when ICs
16
are contained within IC packages. Load
14
is modeled by parasitic capacitance CL representing the combined capacitances of the inputs to ICs
16
in load
14
.
Consider a typical case in which conductor capacitance CB is much less than load capacitance CL. When input voltage V
I
causes switch SW of
FIG. 1
b
to change state, output voltages V
DO
and V
BO
change in the manner generally illustrated by the waveforms of
FIGS. 2
a
-
2
c
. Since capacitance CB is much less than capacitance CL, the combination R
ON
, CL, CB, and LB approximates a series LC resonant circuit which can be (a) underdamped, (b) critically damped, or (c) overdamped according to the value of on resistance R
ON
compared to the reactance of inductance LB.
The waveforms shown in
FIG. 2
a
correspond to the underdamped case in which resistance R
ON
is very low.
FIG. 2
a
illustrates how output voltages V
DO
and V
BO
generally vary when input voltage V
I
makes a high-to-low transition. Driver output voltage V
DO
rises quickly from V
SS
to V
DD
. The effect of conductor inductance LB is to limit the initial flow of current from driver
10
. Consequently, conductor output voltage V
BO
changes slowly at first. However, once current has started flowing through inductance LB, the current continues to flow even when conductor output voltage V
BO
has reached V
DD
. This leads to overshoot in conductor output voltage V
BO
and consequent ringing.
FIG. 2
b
shows waveforms generally representative of the critically damped case in which resistance R
ON
is moderately (but not very) low. The behavior is similar to the underdamped case except that just enough energy is dissipated in resistance R
ON
so that there is little overshoot in conductor output voltage V
BO
, substantially no ringing, and the transition speed for both of output voltages V
BO
and V
DO
is moderately high.
FIG. 2
c
shows waveforms corresponding to the overdamped case where resistance R
ON
is relatively high. Here, the transition speed for both of output voltages V
DO
and V
BO
is low. In particular, conductor output voltage V
BO
takes a comparatively long time to reach the desired V
DD
level.
Both overshoot and low transition speed are generally undesirable signal characteristics. Consequently, the waveforms shown in
FIG. 2
b
often represent the best case for conventional driver
10
. For any of the circuit behaviors depicted in
FIGS. 2
a
-
2
c
, the ringing frequency, the transition speed, and the degree of overshoot depend on the values of elements R
ON
, LB, CB, and CL. While the value of on resistance R
ON
can be controlled during driver design, the values of elements LB, CB, and CL vary from one PWB conductor to another and from one load to another, making it very difficult to achieve the often desired waveforms of
FIG. 2
b
in the typical case where driver design is completed without knowledge of the specific load characteristics.
The energy drawn from the V
DD
power supply approximately equals CV
2
, where V is the potential difference V
DD
−V
SS
, and C is the sum of capacitances CB and CL. Approximately half the supplied energy—i.e., ½CV
2
—
Klarquist Sparkman Campbell & Leigh & Whinston, LLP
Zweizig Jeffrey
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