Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
2000-02-08
2002-05-14
Leja, Ronald W. (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
C257S355000
Reexamination Certificate
active
06388851
ABSTRACT:
The present invention relates to integrated circuits, in particular to electrostatic discharge protection of integrated circuits and to contact pads used in integrated circuits.
BACKGROUND
Electrostatic discharges (ESD) may, as is well known, damage electronic devices, particularly electronic semiconductor devices fabricated on insulating or semi-insulating substrates, such as particularly the kind of devices called integrated circuits. Devices for protecting against ESDs are conventionally incorporated in the input/output paths of most semiconductor devices in order to shunt excessive charge away from the sensitive circuits. In an integrated circuit chip, large metal areas called pads are provided which have free surfaces and area used for connecting the electronic circuits to other electrical devices, i.e., for input to and output from the electronic circuits of a chip. For example, electrically conducting wires can be bonded to such pads. Then ESD protection circuits may be located at and connected to such pads.
When making a connection to a pad, such as a wirebond connection, the downward forces can have a considerable magnitude and can cause delamination of layers below the pad, in particular if metal layers exist there. The forces can also damage pn-junctions located in that area. Thus, electronic circuits such as the ESD circuits cannot easily be located below or straightly under the pad, though such a location of some circuits would generally be advantageous since it would save a significant useful area of the chip of the integrated circuit.
In U.S. Pat. No. 5,514,892, an electrostatic discharge protection device is disclosed having diodes formed in semiconducting wells below a wirebond pad. The pad is through one diode connected to ground and through five diodes connected in series to a supply voltage of 3 V. By the provision of the latter diodes connected in series the integrated circuit is tolerant to 5 V. The diodes are formed below the pad in a pattern having six rectangular areas located in row. This construction, probably especially the particular layout of an intermediate connecting metal layer, is claimed to eliminate the problem of interlayer delamination.
In U.S. Pat. No. 4,750,081, an electrostatic discharge protection circuit is disclosed having diodes located directly beneath the rectangular corners of a wirebond pad. Also, discrete diodes may be formed directly beneath the perimeter or the marginal portion of the pad in a row between the corner diodes, the longitudinal extension of these other diodes being perpendicular to the sides of the pad. The major portion of the pad will thus have no metal layers therebelow, reducing the risk of delamination. Only diodes of a single orientation type are used connecting the metal pad to the substrate by a reverse-biased pn-junction. A protective structure is disclosed in U.S. Pat. No. 5,304,839, the structure not including any resistor in the input or output path.
In input paths of semiconductor devices, often some protection to high input currents is provided, such as an electrical resistance connected in the input path, this resistance limiting the input current. This resistance is conventionally located outside the bonding pad and then occupies some valuable chip area, as is illustrated by the documents cited below.
In U.S. Pat. No. 4,806,999 input pads are protected from electrostatic discharge by two diodes located under the periphery of the pad. The protective diodes are formed by first electrodes connected to the pad and having shapes of relatively narrow strips extending along substantially half the periphery or edge line of the pad. The first electrodes are located connected to or in tubs or wells, which have doping types opposite those of the first electrodes and which form the second electrodes of the diodes and which are intended to be connected to a supply drive voltage or ground. The boundary between the tubs are located in a region not overlaid by the exposed portion of the pad. An input resistor can be included between the pad and the input circuitry.
In U.S. Pat. No. 4,876,584 an integrated circuit is disclosed having terminal pads protected by diodes and transistors. The diodes and transistors are placed horizontally outside the respective pads and have one terminal located at the edge of the pads. A resistor is provided by a resistive path connecting a pad to the remainder of the integrated is circuit. A similar structure having protective diodes and a resistor is disclosed in the published European patent application 0 371 663, the resistor being formed by a metal silicide link placed horizontally outside the pad. Other similar protective structures including a resistor in an input and/or output path are disclosed in U.S. Pat. Nos. 5,808,343, 5,615,073, 5,196,913, 4,730,208 and 4,710,791.
SUMMARY
It is an object of the invention to provide a device for protecting a connection pad of an integrated circuit against excessive positive or negative voltages, the device presupposing no extra processing steps when fabricating the integrated circuit.
It is an object of the invention to provide a device for protecting a connection pad of an integrated circuit against excessive positive or negative voltages having a small parasitic capacitance and having a good tolerance of electric overstress.
It is another object of the invention to provide a connection pad of an integrated circuit which has ESD protection and has a minimum risk of causing latch-up of input/output transistors.
It is another object of the invention to provide a connection pad of an integrated circuit which is protected against ESDs and has a minimum risk of delamination and of damaging pn-junctions of ESD-circuits when exposed to forces incurred when actually making a bonding to the pad, such as wire-bonding.
It is another object of the invention to provide a connection pad of an integrated circuit which has a resistance connected in an input and/or output path and provided in a simple and space-saving way.
Thus, connecting pads such as wirebond pads or pads for “flip-chip” contacting for integrated circuits have protective diodes formed by first electrodes which are connected to the respective pad and which have shapes of relatively narrow strips extending at or along a portion of the periphery or edge line of the pad. The first electrodes have a first doping type and are located connected to or in regions, which have a second doping type opposite the first doping type and form the second electrodes of the diodes and which are intended to be connected to sources of constant potentials capable of absorbing high currents. The location of the first electrodes at the edges of the pads allows that all metal areas required for electrically connecting the first electrodes to the pad can also be located at the edges of the pads. Hence no metal layer beneath the central large portions of the pads Is required. The regions directly below the center portions of the pads can then be made relatively uniform containing e.g. most silicon oxide what reduces the risk of delamination. Also, no pn-junctions have to located beneath said center portions.
The narrow shape of the first electrodes results in a low capacitance of the first electrodes to the second, regions and to other electrically conducting regions of the circuit. The narrow shape also provides a predetermined electrical resistance per unit length resulting in a distribution of possible high currents over the length of the first electrodes. The narrow strips of the first electrodes can be located straightly below a marginal portion of the respective pad and they can also have some portions outside that region, which thus is then will be located below surface portions at the side of the pad. The narrow strips can in many cases be given a sufficient length by making the pads octagonal having angles of substantially 135°. The strip-shaped regions are continuous strips which advantageously should have as smooth a configuration as possible and they should thus have angles not smaller than substanti
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