Electronic devices including indicator control circuits and...

Telecommunications – Transmitter and receiver at same station – Radiotelephone equipment detail

Reexamination Certificate

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Details

C455S550100, C455S575100, C370S211000, C375S238000

Reexamination Certificate

active

06647278

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to indicators for electronic devices and more particularly to control circuits for indicators.
BACKGROUND OF THE INVENTION
Many electronic devices such as radiotelephones and pagers include indicators to alert a user that something has happened or that some action is required. For example, an audible ringer can be used to indicate that a telephone call is being received or that a page has been received. Alternately, a vibrator can be used to provide silent indication.
Known controllers for devices including these indicators, however, may be software intensive. In particular, software operations may be needed to turn the indicator on, and to turn the indicator off. This may be particularly burdensome if the indicator is turned on and off repeatedly for a single indication. This is common, for example, with radiotelephone ringers that are repeatedly turned on and off until either the user answers the call or the calling party hangs up. In such a situation, individual software processing operations may be needed to turn the ringer on and off for each individual ring and to time the intervals that the ringer is turned on and off.
These software processing operations used to control the ringer may reduce time available for other processing operations thereby reducing the performance and/or increasing the complexity of the software as well as the processor running the software. Accordingly, there continues to exist a need in the art for improved circuits and methods to control indicators for electronic devices.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved circuits for controlling electronic indicators and related methods.
This and other objects are provided according to the present invention by storing an off-time value in an off-time register, and storing an on-time value in an on-time register. An indicator control signal is alternatingly enabled for a period of time determined by the on-time value stored in the on-time register and disabled for a period of time determined by the off-time value stored in the off-time register. Accordingly, a processor can load the on- and off-time values in the respective registers and then proceed with other operations so that processor overhead is reduced.
In particular, an electronic device can include an indicator that generates an indication of an event responsive to an indicator control signal, and a processor that generates an indicator off-time value and an indicator on-time value when an indication is desired. The electronic device can also include an indicator control circuit coupled between the processor and the indicator wherein the indicator control circuit receives the indicator off-time value and the indicator on-time value from the processor. More particularly, this indicator control circuit includes on- and off-time registers and an indicator control signal generator. The off-time register stores the off-time value generated by the processor, and the on-time register stores the on-time generated by the processor. The indicator control signal generator alternatingly enables the indicator control signal for a period of time determined by the on-time value stored in the on-time register and disables the indicator control signal for a period of time determined by the off-time value stored in the off-time register. Control of the indicator is thus handled by the indicator control circuit thereby reducing processor operations.
In addition, the indicator control signal can be disabled when the on-time value stored in the on-time register is zero. Accordingly, the indicator control circuit does not perform operations regardless of the off-time value stored in the off-time register. Moreover, the indicator can be turned off by storing an on-time value of zero in the on-time register.
More particularly, the indicator control signal generator can include a timer, a multiplexer, a comparator, and a latching circuit. The timer generates an incrementing elapsed time, and the multiplexer selects one of the on-time value from the on-time register and the off-time value from the off-time register. The comparator compares the incrementing elapsed time with the selected one of the on-time value and the off-time value and the comparator generates a signal when the elapsed time reaches the selected one of the on-time and the off-time values. The latching circuit switches a state of the indicator control signal and resets the timer responsive to the signal that the elapsed time has reached the selected one of the on-time and the off-time values, and the multiplexer selects the other of the on-time value and the off-time value responsive to the signal. Accordingly, the indicator control circuit can be implemented with hardware elements not requiring processor input other than the loading of the register values.
Furthermore, the timer can include a counter coupled to a clock, and the clock can be disabled when either the on-time value stored in the on-time register is zero, or the off-time value stored in the off-time register is zero. When the on-time value is zero, the indicator is turned off so that there is no need to operate the counter. When the off-time value is zero (and the on-time value is non-zero) the indicator is turned on continuously so that there is no need to count the on- and off-time values. In either case, battery drain and/or power consumption can be reduced by disabling the clock when it is not needed.
The processor can also generate an indicator pulse-duty value wherein the indicator control circuit receives this indicator pulse-duty value, and the indicator control circuit can include an indicator pulse-duty register and a pulse width modulation circuit. The indicator pulse-duty register stores the indicator pulse-duty value generated by the processor, and the pulse width modulation circuit modulates a pulse width of the enabled indicator control signal in response to the indicator pulse-duty value stored in the indicator pulse-duty register. The intensity of the enabled indicator control signal can thus be varied responsive to the indicator pulse-duty value thereby varying the intensity of the indication. The modulation circuit can thus be used to reduce or increase power consumed by the indicator thereby reducing or increasing battery drain according to battery charge and/or output desired. For example, the brightness, volume, or intensity of the indication can be controlled as a function of output desired and/or battery charge.
More particularly, the pulse width modulation circuit can include a timer and a comparator. The timer generates an incrementing elapsed time up to a predetermined value and then starts over, the comparator compares the elapsed time and the indicator pulse-duty value, and the pulse width modulation circuit modulates the pulse width of the enabled indicator control signal responsive to the comparison. In addition, the timer can include a counter coupled to a clock, and the clock can be disabled when the indicator control signal is disabled thereby reducing power consumption and/or battery drain when the clock is not needed.
In addition, the electronic device can include a transceiver coupled to the processor wherein the transceiver transmits and receives radio communications under control of the processor, and the indicator can be a buzzer, a ringer, a light, a vibrator, or an annunciator.
The devices and methods of the present invention can thus be used to control an indicator with reduced interaction from a device processor. In particular, the processor need only load registers with values defining the operating parameters for the indicator, and the indicator control circuit of the present invention generates the actual control signals for the indicator. In particular, on-time and off-time values can be stored in respective registers. Processor overhead can thus be reduced.


REFERENCES:
patent: 5408698 (1995-04-01), Serizawa et al.
patent: 5414862 (1995-05-01), Suzuki et al.
patent: 5638054 (1997-06-

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