Electronic device wafer level scale packages and fabrication...

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S110000, C438S114000, C438S460000, C438S461000, C438S462000, C438S463000, C438S464000, C438S465000, C257SE21523

Reexamination Certificate

active

07981727

ABSTRACT:
Electronic device wafer level scale packages and fabrication methods thereof. A semiconductor wafer with a plurality of electronic devices formed thereon is provided. The semiconductor wafer is bonded with a supporting substrate. The back of the semiconductor substrate is thinned. A first trench is formed by etching the semiconductor exposing an inter-layered dielectric layer. An insulating layer is conformably deposited on the back of the semiconductor substrate. The insulating layer on the bottom of the first trench is removed to create a second trench. The insulating layer and the ILD layer are sequentially removed exposing part of a pair of contact pads. A conductive layer is conformably formed on the back of the semiconductor. After the conductive layer is patterned, the conductive layer and the contact pads construct an S-shaped connection. Next, an exterior connection and terminal contact pads are subsequently formed.

REFERENCES:
patent: 6624505 (2003-09-01), Badehi
patent: 6972480 (2005-12-01), Zilber et al.
patent: 7271466 (2007-09-01), Noma et al.
patent: 7340181 (2008-03-01), Prabhu et al.
patent: 7394152 (2008-07-01), Yu et al.
patent: 7399683 (2008-07-01), Noma et al.
patent: 7413931 (2008-08-01), Noma et al.
patent: 7557017 (2009-07-01), Yamada et al.
patent: 2001/0018236 (2001-08-01), Badehi
patent: 2003/0179415 (2003-09-01), Yasuda
patent: 2005/0009238 (2005-01-01), Okigawa
patent: 2005/0095750 (2005-05-01), Lo et al.
patent: 2005/0208735 (2005-09-01), Noma et al.
patent: 2007/0145420 (2007-06-01), Okada et al.
patent: 2008/0164553 (2008-07-01), Lin et al.
patent: 2008/0191343 (2008-08-01), Liu

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Electronic device wafer level scale packages and fabrication... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Electronic device wafer level scale packages and fabrication..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electronic device wafer level scale packages and fabrication... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2654885

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.