Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays
Reexamination Certificate
1999-11-04
2003-03-18
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
C257S208000
Reexamination Certificate
active
06534803
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an electrode forming technique, and more specifically to an electronic device and a semiconductor device having a micro interconnection, and a method for forming an electrode.
Referring to
FIG. 4
, there is shown a layout diagram of bit lines and word lines under bit lines in a memory cell array of a conventional DRAM (dynamic random access memory). Ordinarily, the bit lines
2
and
3
A in the DRAM memory cell array are periodically and densely located with a line width “A” and a line space “C” both of a minimum standardized size, and at one end of the memory cell array, a half number of bit lines
3
A are caused to extend outwardly into a peripheral circuit section. Therefore, at the outside of the memory cell array, the density of the bit lines becomes a half of the density in the memory cell array, and the periodical pattern of the line and space changes. In the peripheral circuit section, the bit line
3
A is connected through a contact
4
to an underlying diffused layer (not shown).
For example, Japanese Patent Application Pre-examination Publication Nos. JP-A-05-283437, and JP-A-06-175348 disclose a conventional method for forming a wiring or interconnection pattern. Here, JP-A-05-283437 and JP-A-06-175348 will be called a “first prior art” and a “second prior art”, hereinafter, respectively.
The first prior art is a method for forming, in an active layer region, a gate pattern for a transistor having a structure in which a gate electrode is interposed between a source electrode and a drain electrode. At an outside of the active layer region but in the vicinity of the source electrode and the drain electrode, dummy patterns interposing a gate electrode therebetween are formed of a source/drain electrode metal, to have the same thickness as that of the source electrode and the drain electrode. Thereafter, a photoresist film is formed, and then is patterned for forming the gate pattern. Alternatively, the dummy patterns can be formed of a Schottky metal or an insulator in place of the source/drain metal. Namely, since the dummy patterns formed of the source/drain electrode metal and having the same thickness as that of the source electrode and the drain electrode were formed in the vicinity of the source electrode and the drain electrode, it is possible to easily uniformly and thinly form a gate finger pattern in the active layer region without increasing the number of steps in process. In addition, if the dummy patterns are formed of the Schottky metal, the characteristics of the transistor is elevated by a guard ring effect. If the dummy patterns are formed of the insulator, it is no longer necessary to pay attention to a leak current which is caused by adding the dummy pattern and which becomes one cause for a characteristics deterioration of the transistor, with the result that all of the advantage attributable to the shortening of the gate length can be enjoyed.
Referring to
FIG. 5
, there is shown an interconnection pattern in the second prior art. As shown in
FIG. 5
, the second prior art is a resist pattern forming method, in which when a photo mask used for a projection exposure has a synthesized graphic pattern composed of a first pattern
5
having a width W {≦&Lgr;/(2×NA)} where &Lgr; is an exposure light wavelength and NA is a numerical aperture of a projection lens, and a second pattern
6
coupled to the first pattern, a step difference between the first pattern and the second pattern being not less than W/3, and a synthesized graphic pattern has a width expanded pattern
7
obtained by expanding the width of the first pattern over a predetermined length and at least at one side from the connection between the first pattern and the second pattern by {a×W} where 0.07≦a≦0.28. In addition, the coherence degree of the projecting exposure light is not greater than 0.4, and the photo mask is a phase-shift mask for controlling the phase of a transmitted light.
With this arrangement, it is possible to prevent the thinning of the pattern at a width or size changing portion, which was a problem in the prior art when a pattern not exceeding a resolution limit is formed by a phase shift mask. Therefore, this method can be applied for forming a complicated pattern which is used in an actual device and which is near to the resolution limit. When a semiconductor device was fabricated by using this mask, the pattern could be microminiaturized in comparison with the conventional pattern, and therefore, the device area could be reduced.
However, under an exposure condition for lithography necessary to form fine patterns near to the resolution limit and located densely to each other, as in a memory cell array, a light intensity becomes relatively strong in a sparse pattern region, with the result that an overexposure occurs. Thus, the thinning of the resist pattern and an insufficient resolution become easy to occur.
In order to overcome this problem, the first prior art proposes to form an underlying dummy pattern at the outside of the interconnection region. However, if the density of the interconnections becomes a problem as shown in
FIG. 4
, the first prior art is not effective. Particularly, in a lead-out portion for pulling out the bit lines from the inside to the outside of the memory cell array section, the bit line is thinned as shown by dotted line in
FIG. 4
or broken in an extreme case, with the result that the yield of production drops.
On the other hand, the second prior art avoids influence of a diffracted light by providing the width expanded portion
7
at the coupling portion between the pattern
5
having a narrow line width and the pattern
6
having a relatively wide line width. However, since the interconnection pattern ordinarily has a constant line and space, the influence itself of the diffracted light is small. In addition, if the line width is expanded at a region where the density changes, a short-circuiting becomes easy to occur between adjacent interconnections. Therefore, the second prior art cannot be applied.
BRIEF SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to overcome the above mentioned problem of the prior art.
Another object of the present invention is to provide an electronic device, a semiconductor device, and an electrode forming method, which are capable of preventing the thinning or the break of bit lines in a region where the density of periodically located interconnections changes, thereby to improve the yield of production.
The above and other objects of the present invention are achieved in accordance with the present invention by an electronic device having a high interconnection density section where interconnections are located periodically and densely and a low interconnection density section where interconnections are located periodically but sparsely, wherein in the low interconnection density section, the interconnections have a portion which has a line width “B” larger than the line width “A” of the interconnections in the high interconnection density section, and which is separated from the high interconnection density section by a predetermined distance on the order of a minimum standardized size “D”, and wherein a line space “C” in the high interconnection density section and the minimum standardized size “D” fulfill the relation of C≦D≦2×C.
According to another aspect of the present invention, there is provided a semiconductor device having a memory cell array section having a high interconnection density where interconnections are located periodically and densely and a low interconnection density section where selected but not all ones of the interconnections in the memory cell array section are pulled out from the memory cell array section and are located periodically but sparsely. In the low interconnection density section, the selected but not all interconnections have a portion which has a line width “B” larger than the line width “A” of the interconnections i
Cao Phat X.
NEC Corporation
Young & Thompson
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