Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With peripheral feature due to separation of smaller...
Patent
1998-12-21
1999-12-14
Thomas, Tom
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With peripheral feature due to separation of smaller...
257618, 257621, 257622, 257777, 257778, H01L 2331
Patent
active
060021632
ABSTRACT:
Top die pads are electrically relocated by forming holes through a semiconductor wafer between device active regions. An electrically insulating layer is formed over all exposed surfaces of the wafer, including within the holes, and openings are made in the insulating layer for access to the top interconnection pads. The wafer and holes are metallized and patterned to form bottom interconnection pads electrically connected to corresponding top interconnection pads by metallization extending within the holes. A dicing saw having a kerf width less than the diameter of the holes is employed to separate the individual devices. For accurate position alignment of repatterned die, an alignment structure, such as projecting pins or an egg crate structure, engages the die, and alignment pads can be patterned on the die.
REFERENCES:
patent: 4783695 (1988-11-01), Eichelberger et al.
patent: 4835704 (1989-05-01), Eichelberger et al.
patent: 4836435 (1989-06-01), Napp et al.
patent: 4878991 (1989-11-01), Eichelberger et al.
patent: 4897153 (1990-01-01), Cole et al.
patent: 4930216 (1990-06-01), Nelson
patent: 4933042 (1990-06-01), Eichelberger et al.
patent: 4984358 (1991-01-01), Nelson
patent: 5094709 (1992-03-01), Eichelberger et al.
patent: 5118027 (1992-06-01), Braun et al.
patent: 5161093 (1992-11-01), Gorczyca et al.
patent: 5200810 (1993-04-01), Wojnarowski et al.
patent: 5237434 (1993-08-01), Feldman et al.
patent: 5239191 (1993-08-01), Sakumoto et al.
patent: 5324687 (1994-06-01), Wojnarowski
patent: 5352629 (1994-10-01), Paik et al.
patent: 5353195 (1994-10-01), Fillion et al.
patent: 5353498 (1994-10-01), Fillion et al.
patent: 5366906 (1994-11-01), Wojnarowski et al.
patent: 5455459 (1995-10-01), Fillion et al.
patent: 5492586 (1996-02-01), Gorczyca
patent: 5497033 (1996-03-01), Fillion et al.
patent: 5546654 (1996-08-01), Wojnarowski et al.
patent: 5684677 (1997-11-01), Uchida et al.
patent: 5703400 (1997-12-01), Wojnarowski et al.
patent: 5818404 (1998-10-01), Lebby et al.
Agosti Ann M.
Breedlove Jill M.
General Electric Company
Thai Luan
Thomas Tom
LandOfFree
Electronic device pad relocation, precision placement, and packa does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Electronic device pad relocation, precision placement, and packa, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electronic device pad relocation, precision placement, and packa will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-866045