Electronic device package and method of manufacture

Details Electronic device package and method of manufacture Electronic device package and method of manufacture

2011-08-09

2011-08-09

Graybill, David E (Department: 2894)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Metallic housing or support

C438S126000, C438S127000, C438S612000, C438S613000, C438S928000

Reexamination Certificate

active

07993981

ABSTRACT:
A method of manufacturing an electronic device package. Coating a first side of a metallic layer with a first insulating layer and coating a second opposite side of the metallic layer with a second insulating layer. Patterning the first insulating layer to expose bonding locations on the first side of the metallic layer, and patterning the second insulating layer such that remaining portions of the second insulating layer on the second opposite side are located directly opposite to the bonding locations on the first side. Selectively removing portions of the metallic layer that are not covered by the remaining portions of the second insulating layer on the second opposite side to form separated coplanar metallic layers. The separated coplanar metallic layers include the bonding locations. Selectively removing remaining portions of the second insulating layer thereby exposing second bonding locations on the second opposite sides of the separated coplanar metallic layers.

REFERENCES:
patent: 2008/0258273 (2008-10-01), Liang et al.
patent: 2008/0268578 (2008-10-01), Shimanuki et al.
patent: 2009/0034225 (2009-02-01), Shoji et al.
patent: 2009/0053498 (2009-02-01), Matsuura et al.
patent: 2009/0068794 (2009-03-01), Shen et al.
patent: 2009/0068797 (2009-03-01), Shen et al.
patent: 2009/0283882 (2009-11-01), Hsieh et al.
patent: 2010/0129964 (2010-05-01), Goh et al.

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