Electronic device manufacturing method

Metal working – Method of mechanical manufacture – Electrical device making

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C029S825000, C029S830000, C029S832000, C029S840000, C029S846000, C438S623000, C438S634000, C438S637000, C438S638000, C438S687000

Reexamination Certificate

active

06898851

ABSTRACT:
It is an object to provide a semiconductor device having a buried multilayer wiring structure in which generation of a resolution defect of a resist pattern is suppressed and generation of a defective wiring caused by the resolution defect is reduced. After a via hole (7) reaching an etching stopper film (4) is formed, annealing is carried out at 300 to 400° C. with the via hole (7) opened. As an annealing method, it is possible to use both a method using a hot plate and a method using a heat treating furnace. In order to suppress an influence on a lower wiring (20) which has been manufactured, heating is carried out for a short time of approximately 5 to 10 minutes by using the hot plate. Consequently, a by-product staying in an interface of an upper protective film (6) and an interlayer dielectric film (5) having a low dielectric constant and a by-product staying in an interface of the etching stopper film (4) and the interlayer dielectric film (5) having a low dielectric constant are discharged so that an amount of the residual by-product can be decreased.

REFERENCES:
patent: 6291891 (2001-09-01), Higashi et al.
patent: 6368951 (2002-04-01), Higashi et al.
patent: 6383907 (2002-05-01), Hasegawa et al.
patent: 6440844 (2002-08-01), Takagi et al.
patent: 6509273 (2003-01-01), Imai et al.
patent: 6566283 (2003-05-01), Pangrle et al.
patent: 6624061 (2003-09-01), Aoki
patent: 6723631 (2004-04-01), Noguchi et al.
patent: 6743713 (2004-06-01), Mukherjee-Roy et al.
patent: 6765283 (2004-07-01), Umemoto
patent: 6787446 (2004-09-01), Enomoto et al.
patent: 2000-269326 (2000-09-01), None
S. M. Jang, et al., “Integration of CU and Low-K Material for Dual-Damascene Process”, Semiconductor Technology, (ISTC 2001), vol. 1, pp. 485-493.
K. Higashi, et al., “A Manufacturable Copper/Low-K SiOC/SiCN Process Technology for 90NM-Node High Performance eDRAM”, Proceedings of the 2002 International Interconnect Technology Conference, pp. 15-17.
M. Fayolle, et al., “Integration of Cu/SiOC in Dual Damascene Interconnect for 0.1μm Technology Using A New SiC Material as Dielectric Barrier”, Proceedings of the 2002 International Interconnect Technology Conference, pp. 39-41.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Electronic device manufacturing method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Electronic device manufacturing method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electronic device manufacturing method will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3390466

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.