Data processing: generic control systems or specific application – Specific application – apparatus or process – Electrical power generation or distribution system
Reexamination Certificate
2000-03-31
2002-10-08
Picard, Leo (Department: 2125)
Data processing: generic control systems or specific application
Specific application, apparatus or process
Electrical power generation or distribution system
C700S298000, C700S297000
Reexamination Certificate
active
06463362
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to electronic devices connected to, for example, P1394 serial buses, and in particular to operating mode control technology for preventing hang-ups during bus resets.
Systems where electronic devices such as personal computers, digital tape recorders and digital television receivers are connected using a P1394 serial bus and packets for digital video signals, digital audio signals and control signals are sent and received between these electronic devices can be considered.
An example of this kind of system is shown in FIG.
4
. In
FIG. 4
, the electronic devices A to D are the aforementioned personal computers and digital video tape recorders etc. P1394 serial bus cables
111
,
112
and
113
then make connections across the ports P of the electronic devices A and B, B and C and C and D. These electronic devices are referred to as nodes in the following specification.
A pair of shielded twisted-pair cables (not shown in the drawings) are provided within these P1394 serial cables. Of this pair of twisted-pair cables, one pair is used for data transmission and the other pair is used for strobe signal transmission. Further, each node outputs a bias voltage for one twisted-pair cable and the bias voltage is detected on the other twisted-pair cable.
As shown in
FIG. 4
each of the nodes is equipped with a physical layer controller (PHY)
114
, a link layer controller (LINK)
115
and a central processing unit (hereinafter referred to as “CPU”)
116
as a basic structure for carrying out communications on the P1394 serial bus. The physical layer controller
114
has functions for bus initialization, data encoding/decoding, arbitration and bias voltage output/detection etc. Further, the link layer controller
115
has link layer controller functions for error correction code generation/detection and packet generation/detection etc. The CPU
116
has an application layer function.
With the communication system constructed in this way, when the power supply of node A goes from off to on with the nodes B to D on in a normal operating state, a power supply voltage is supplied to the physical layer controller
114
, the link layer controller
115
and the CPU
116
of the node A and normal operation begins.
At this time, the physical layer controller
114
outputs a bias voltage onto the twisted-pair cable of the P1394 serial bus cable
111
. This bias voltage is detected by the physical layer controller of node B connected directly by the P1394 serial bus cable
111
. As a result, the node B knows that node A is connected by the P1394 serial bus cable
111
.
In this way, if a new node is connected to the bus, a bus reset occurs when the bias voltage outputted to the bus by the physical layer controller of this node is detected by the physical layer controllers of the other nodes and physical address allocation for each node by the physical layer controllers of each node is automatically completed within at least 170 &mgr;sec. The details of this point are defined in the specification for the IEEE-P1394 serial bus and a detailed description is therefore omitted.
When a bus reset occurs and physical address allocation for each of the nodes is complete, the nodes B to D commence transactions necessary at the time of bus reset decided by the protocol. For example, a packet for interrogating as to what type of equipment etc. the node A belongs to is transmitted. The transaction is then completed by the node A correctly transmitting a packet in response to the interrogation.
However, usually, the CPU
116
has to carry out various internal initialization processes directly after the power supply is thrown. Turned on the time is necessary for changes depending on what kind of machine the node is and what process the node is carrying out, but is usually from a few tens of milliseconds to a few seconds. Other nodes cannot then receive response packets from node A because node A cannot respond to interrogations from other nodes during this time. The node A therefore experiences a time-out and the system may hang up.
For example, in order to carry out Isochronous (hereinafter abbreviated to “Iso”) communications, a transaction is generated for carrying out confirmation of the communication channel and band for a uniquely designated resolver node when resetting the bus. However, if the node A becomes the resolver node, other nodes cannot start ISO communication until the node A completes initialization.
In order to resolve these kinds of problems, the object of the present invention is to provide an electronic device and operating mode control method which do not cause the communications system to hang-up when the power supply is thrown.
SUMMARY OF THE INVENTION
In order to achieve this object, according to the present invention, an electronic device is employed in a system where packets are sent and received between a plurality of electronic devices connected by a bus, in such a manner that a bias voltage is not outputted to the bus in a first operating mode operated in from when a power supply is thrown until an internal initialization process is complete and a bias voltage is outputted to the bus in a second operating mode operated in after the initialization process is complete.
The initialization process can be an initialization of internal information necessary for transmitting and receiving packets. The electronic device can have a physical layer controller for outputting the bias voltage and the initialization process can be carried out by a central processing unit.
Further, according to the present invention, an operating mode control method for an electronic device employed in a system for carrying out communication between a plurality of electronic devices connected by a bus, comprises the steps of configuring the electronic device in such a manner that a bias voltage is not outputted to the bus in a first operating mode operated in from when a power supply is thrown until an internal initialization process is complete and outputting a bias voltage to the bus in a second operating mode operated in after the initialization process is complete.
The initialization process can be an initialization of internal information necessary for transmitting and receiving packets.
According to the present invention, a bias voltage is not outputted to the bus from when the power supply is thrown until an internal initialization process is complete and a bias voltage is outputted to the bus after an internal initialization process is complete.
REFERENCES:
patent: 4149241 (1979-04-01), Patterson
patent: 5327428 (1994-07-01), Van As et al.
patent: 5394556 (1995-02-01), Oprescu
patent: 5537600 (1996-07-01), Fuoco et al.
patent: 5590341 (1996-12-01), Matter
Kosowski Alexander J.
Picard Leo
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