Electronic data processing system overlaid jump mechanism

Details Electronic data processing system overlaid jump mechanism Electronic data processing system overlaid jump mechanism

1985-12-16

1988-04-05

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 922

Patent

active

047362928

ABSTRACT:
A series of instructions N, N+1, N+2, etc. are issued by an instruction buffer 14 at a fixed clock rate in a pipelined method to parallel instruction flow path 6 and control word flow path 8, each path including a serial coupled holding register 20, 21, an instruction register 18, 19 and a function register 16, 17. If instruction N is a jump instruction, it and the related control word, when stored in the function registers 16, 17 causes the jump target instruction and the related control word of the jump instruction N to be entered into the holding register 20, 21. If the jump instruction N jump conditions are satisfied, the jump target instruction and related control word are written into the instruction registers 18, 19 and then into the function registers 16, 17 to be executed by the associated system.

REFERENCES:
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patent: 4156900 (1979-05-01), Gruno et al.
patent: 4245302 (1981-01-01), Amdahl
patent: 4247893 (1981-01-01), Anderson et al.
patent: 4451884 (1984-05-01), Heath et al.
patent: 4667290 (1987-05-01), Goss et al.
patent: 4691279 (1987-09-01), Danilenko et al.

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