Electrical pulse counters – pulse dividers – or shift registers: c – Applications – Including memory
Reexamination Certificate
1999-03-04
2001-03-27
Wambach, Margaret R. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Applications
Including memory
C377S049000
Reexamination Certificate
active
06208705
ABSTRACT:
TECHNICAL FIELD
This invention relates to an electronic counter incorporated in electronic memory devices integrated on seminconductors.
BACKGROUND OF THE INVENTION
As is well known the procedures involved in programming, reading and erasing the contents of memory cells in a semiconductor-integrated electronic memory device are run as predetermined sequences of operations handled by suitable algorithms.
These algorithms are effective to time the several steps of such operations, but require the assistance of some counters to calculate the durations of various time intervals, the number of times that a given operation has been executed, or the value of an address bus.
The counters can take up a considerable amount of circuit area in the memory device. Also, the time taken to complete the various counts can affect the execution rate of the program and erase algorithms.
Thus, counters intended for use within a memory device normally require accurate specific designing.
As mentioned above, in executing an algorithm through the memory device, certain counts must be performed as detailed hereinbelow.
1) Counting the time intervals; this will serve to either set the duration of a signal pulse or establish wait intervals.
2) Counting the number of attempted executions of certain operations: this will serve to decide whether, following a predetermined number of iterations, any subsequent operation is to be carried out or an error signal is to be issued.
3) Calculating the value of a current address: this will serve to either repeat the same operation at all the memory locations or at a predetermined set of addressable locations in a particular algorithm.
It is readily evinced from the foregoing considerations the a proper execution of the algorithms involves counts of different nature, leading to different and values.
For instance, the program time is on the order of a few microseconds for the address of a memory location, whereas the erase time for the smallest addressable portion is on the order of one second. In addition, the number of program attempts may amount to a few tens, whereas the number of case attempts may be on the order of a few hundreds.
As for the addresses, it may be possible to program a full section of the memory array or the whole memory array, but in the erase mode, one or more sections may have to be erased, and each memory location verified in consequence; this means that all the addresses must be scanned.
The counting base of an electronic counter is binary, and the duration of the count is set by the period of its synchronization or “clock” signal.
For calculating the time intervals, the clock period must be known because the intervals are computed as multiples of that period.
For counts which are not based on time, only the counter range need to be defined.
Some examples are given hereinbelow.
The number of a memory location program attempts can be arranged to be at least fifteen, before an error signal is issued. In this case, a four-bit counter would be required, since the nearest binary value to fifteen is 2
4
.
If the memory device comprises a 1 Mbyte array, and the array is organized into bytes, then an address counter of no less than 20 bits must be available, for 2
20
=1,048.576.
If a program pulse duration can be 5 &mgr;s, while the erase pulse can have a duration of 10 ms, then 50 clock pulses would become necessary to span the first count and 100,000 clock pulses to span the second count, where am clock period is 100 ns. Accordingly, a six-bit (2
6
=64) counter would be needed for the first count, and a seventeen-bit (2
17
=131,072) counter for the second count.
It should be fiber considered that, in an electrically erasable non-volatile memory, the erasing of a section of the memory array may have to be discontinued in order to enable the programming of one or more locations in another section. In this not unlikely circumstance, the counts must be replicated because the counts for the erase operation need to be stopped and stored in order to effect the counts for the programming operation.
But even the programming may have to be discontinued, to allow a read operation from some other memory location.
Finally, there exists a pressing demand for electrically erasable non-volatile memory devices wherein the user can request reading from plural adjacent memory locations by only entering address of the first location (in the so-called “burst model” access). In this case, the device should be capable of calculating the next addresses from the entered one.
To summarize, a memory device of the type described hereinabove may require as many as seven different counters, namely:
a program time counter;
an erase time counter;
a program attempt counter;
an erase attempt counter;
a program address counter;
an erase address counter; and
a burst mode address counter.
A known solution which has been used in the past provided all of these seven counters within a memory device. An obvious advantage of this solution is that all the counts to be performed are available in an independent manner. However, a significant disadvantage comes from the concurrent use of a large circuit area.
A more recent solution provides for the use of but one counter interfaced with a plurality of latch registers.
To activate or deactivate the counting, the counter is delivered an enable signal ENABLE from the memory internal logic circuitry. The enable signal increases by “1” the contents of the first count cell on the leading edge of the clock signal.
The counter has several outputs which supply the current count value at each time.
To effect the various counts at the appropriate times, the contents of a first latch is replicated into the counter, and the result of the count is replicated into a second latch.
The accompanying
FIG. 1
shows schematically a convention single counter for memory devices. The counter includes a count cell which consists of a half-adder type of summing block having a flip-flop cascade connected thereto.
The half-adder cell has a first count output connected to the flip-flop and a second, carry-over output CARRYOUT liked directly to an output of the couter.
The flip-flop output is input to both a first flip-flop and a second flip-flop outside the counter. The parallel-connected flip-flops may be provided in any desired number. The individual outputs of both these external flip-flops are connected to an input of he half-adder cell.
The counter construction is completed by a second, carry-over input CARRYIN which represents an enable signal to the first cell and the signal CARRYOUT to the next cell.
As an example, suppose that the times and the erase attempts are to be counted. During a first period of the clock pulse, the contents of the count cell will be replicated into the first external flip-flop storing the number of attempts, whereas during a second period of the clock pulse, the contents of the second external flip-flop will be replicated into the count cell. The count proper requires one or more clock periods.
Should it become necessary to start a count of the attempts at this stage, two additional clock pulses would be needed before the count can be started.
In essence, a loss in performance is traded for a reduced occupation of circuit area, due to the longer time taken to execute the various algorithum.
Modem memory devices involve a fairly large number of counts, and this reflects in increased complexity of the control logic.
SUMMARY OF THE INVENTION
An embodiment of this invention provides a single electronic counter for an electrically erasable non-volatile memory device integrated on a semiconductor, which counter has suitable functional and constructional features to shorten the execution times for the various programming and erasing algorithms, allows of operation in the burst mode, and is low in circuit area requirement. This effectively overcomes the drawbacks with which the prior art approaches are still beset.
The counter has a single count cell associated with a single master portion shared by a plurality of slave reg
Ferrario Donato
Ghezzi Stefano
Lomazzi Guido
Maccarrone Marco
Galanthay Theodore E.
Iannucci Robert
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
Wambach Margaret R.
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