Data processing: vehicles – navigation – and relative location – Vehicle control – guidance – operation – or indication – Vehicle diagnosis or maintenance indication
Reexamination Certificate
1999-09-08
2001-06-05
Chin, Gary (Department: 3661)
Data processing: vehicles, navigation, and relative location
Vehicle control, guidance, operation, or indication
Vehicle diagnosis or maintenance indication
C701S033000, C701S076000, C701S092000, C303S122050
Reexamination Certificate
active
06243629
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
This invention relates to an electronic control unit for automotive vehicles, and more particularly, such an electronic control unit for performing a fail-safe function so as to control systems or apparatuses to be controlled by the control unit with improved reliability.
2. Prior Art
An anti-lock braking system (hereinafter referred to as “ABS”) which is conventionally widely used in automotive vehicles operates to release the brake pressure of a brake system of the automotive vehicle upon detecting of the start of locking of a wheel or wheels in response to data from a wheel speed sensor and a vehicle speed estimated from the data, to thereby restrain slippage of the vehicle wheel (s), thus enhancing the braking function and hence maintaining stability of the vehicle so that the vehicle can be stopped safely. In the anti-lock system, it is important to enhance the reliability of the system itself. To this end, conventionally, an electronic control unit (hereinafter referred to as “ECU”) is employed in the ABS system, which is provided with two central processing units (hereinafter referred to as “CPUs”) for synchronously performing the same arithmetic processing in response to a common input signal and a common clock signal, wherein only when results of the arithmetic processing executed by the both CPUs are the same, an output signal is generated and delivered to a system or an apparatus to be controlled, thus enhancing the reliability of the system, as disclosed in Japanese Patent Publication (Kokoku) No. 4-31123. That is, in the system provided with two CPUs, one CPU plays a role of a redundancy circuit for the other CPU to provide a fail-safe control.
This conventional ECU, however, is costly because the ECU must be provided with two CPUs.
To overcome this drawback, there has been proposed an improvement on the above dual CPU system, wherein the relationship between the two CPUs is set such that one CPU works as a main CPU while the other CPU works as a sub CPU, as disclosed in Japanese Laid-Open Patent Publication (Kokai) No. 2-296570. The main CPU executes a main original control of a system to be controlled while the sub CPU monitors whether the main CPU is operating normally or not. Therefore, the sub CPU is merely provided with logic circuits which are necessary for monitoring the operation of the main CPU and executes a simpler arithmetic processing compared to that of the main CPU.
The conventional ECU which is provided with the main CPU and the sub CPU will be explained in detail hereinbelow with reference to
FIG. 1
schematically showing the arrangement of the conventional ECU for a automotive vehicle.
As shown in
FIG. 1
, the ECU is provided with a main CPU
1
and a sub CPU
2
. An output of a wheel speed sensor
3
is connected to an input of the main CPU
1
by way of a signal line
4
, while an input of an OR circuit
6
is connected to an output of the main CPU
1
by way of a signal line
5
. Another output of the wheel speed sensor
3
is connected to an input of the sub CPU
2
by way of a signal line
7
, and another input of the OR circuit
6
is connected to an output of the sub CPU
2
by way of a signal line
25
. An output of the OR circuit
6
is connected to a fail-safe relay
8
and an alarm lamp
9
by way of a signal line
11
. The fail-safe relay
8
, when operated, cuts off the supply of electric power to a solenoid valve
10
as explained later, and the alarm lamp
9
, when operated, warns an occurrence of abnormality in the ABS control to the driver, as explained later.
The main CPU
1
has a memory means
12
which stores control programs for carrying out logical operations executed by the main CPU
1
.
The main CPU is a microprocessor provided with a CPU core
13
which performs arithmetic processing on control programs. The CPU core
13
includes a wheel speed signal-processing block
14
which executes necessary processing such as filtering of a wheel speed signal WS generated by the wheel speed sensor
3
and calculates a vehicle speed signal VS based on the filtered signal, an ABS control block
15
which executes ABS control processing in response to the wheel speed signal WS and the vehicle speed signal VS, and a solenoid valve control block
16
which controls the solenoid valve
10
in response to a control signal fed from the ABS control block
15
. The output of the main CPU
1
is connected to the solenoid valve
10
by way of a communication line
17
. The solenoid valve
10
regulates the brake pressure of a brake system of the vehicle applied to wheels in response to the control signal fed from the solenoid valve control block
16
. The operative state of the solenoid valve
10
is transmitted to the main CPU
1
and the sub CPU
2
by way of communication lines
18
and
19
.
The sub CPU
2
is a microprocessor which monitors the entire system including the main CPU. The sub CPU
2
is provided with a CPU core
20
which corresponds to the CPU core
13
of the main CPU
1
. The CPU core
20
includes a vehicle speed signal-processing block
14
′, an ABS partial control block
21
and a solenoid valve-monitoring block
22
which correspond, respectively, to the wheel speed signal processing block
14
, the ABS control block
15
and the solenoid valve control block
16
which are included in the CPU core
13
.
The wheel speed signal-processing block
14
′ executes the same processing as that of the wheel speed signal-processing block
14
of the main CPU
1
. The ABS partial control block
21
executes arithmetic processing necessary exclusively for monitoring the operation of the ABS control block
15
of the CPU
1
but does not execute ABS control. The solenoid valve-monitoring block
22
executes only monitoring of the operation of the solenoid valve
10
but does not execute control of the operation of the solenoid valve
10
.
The main CPU
1
and the sub CPU
2
are connected with each other by way of communication lines
23
and
24
for transmitting and receiving data therebetween.
The operation of the conventional ECU constructed above will be described hereinbelow.
The wheel speed signal WS is fed both to the main CPU
1
and the sub CPU
2
from the wheel speed sensor
3
by way of the respective signal lines
4
and
7
. Upon receiving the signal WS, the main CPU
1
executes the following processing based on control programs stored in the memory means
12
:
The wheel speed signal processing unit
14
processes the wheel speed signal WS from the wheel speed sensor
3
. During this processing, if an abnormality is found in the output from the wheel speed sensor
3
, the processing unit
14
delivers a fail-safe signal to the OR circuit
6
by way of the signal line
5
.
The ABS control block
15
executes arithmetic processing related to the ABS control in response to the wheel speed signal WS processed by the wheel speed signal processing unit
14
and the vehicle speed signal VS estimated from the wheel speed signal WS. During this processing, if an abnormality is found in the operation of the ABS control block
15
, the control block
15
delivers a fail-safe signal to the OR circuit
6
by way of the signal line
5
.
The solenoid valve control block
16
operates based on results of the calculation by the ABS control block
15
and a response from the solenoid valve
10
which will be described later, to deliver a control signal to the solenoid valve
10
by way of the communication line
17
so as to control the operation of the solenoid valve
10
. During this processing, if an abnormality is found in the control of the solenoid valve
10
, the control block
16
delivers a fail-safe signal to the OR circuit
6
by way of the signal line
5
.
The solenoid valve
10
regulates the brake pressure in response to the control signal transmitted from the solenoid control block
16
and delivers a signal indicative of its own operative state which reflects its response to the control signal to the main CPU
1
and the sub CPU
2
, respectively, by w
Sugimoto Yoshiyuki
Takayama Yusuke
Chin Gary
Frishauf, Holtz Goodman, Langer & Chick, P.C.
Honda Giken Kogyo Kabushiki Kaisha
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