Electronic computer which executes squash branching

Boots – shoes – and leggings

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395800, 364DIG1, 3642318, 36423223, 3642613, 3642615, 364263, G06F 938

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active

054468493

ABSTRACT:
An electronic computer according to this invention is capable of executing a plurality of instructions simultaneously. It is characterized by comprising a flag adding section for judging whether or not each of a plurality of instruction is either a delayed branch instruction or a squash branch instruction, and based on the results, adding a flag indicating an abort condition to each instruction, and a command execute abort section for aborting execution of each instruction on the basis of whether or not the flag added to each instruction to indicate the abort condition and each branch instruction hold true.

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Lilja, David J., "Reducing the Branch Penalty in Pipelined Processors," Computer, Jul. 1988, pp. 47-55.
IBM J. Res. Develop., vol. 34, No. 1, Jan. 1990, pp. 37-58, G. F. Grohoski, "Machine Organization of the IBM RISC System/6000 Processor".
1989 IEEE International Conference on Computer Design: VLSI in Computers & Processors, Oct. 1989, Piyush Patel, et al., "Architectural Features of the i860(TM)--Microprocessor RISC Core and On-Chip Caches", pp. 385-390.
The 13th Annual International Symposium on Computer Architecture, Jun. 1986, Scott McFarling, et al., "Reducing the Cost of Branches", pp. 396-403.

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