Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates
Reexamination Certificate
2007-05-08
2007-05-08
Ghyka, Alexander (Department: 2812)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
C438S484000, C257SE21309, C257SE21415
Reexamination Certificate
active
10421368
ABSTRACT:
A method is provided for fabricating integrated electronic components. According to the method, an initial structure is produced on the surface of a first substrate. This initial structure incorporates a defined pattern formed from volumes of differentiated materials. At least part of the initial substrate that includes the defined pattern is transferred onto a second substrate, preferably by inverting the first substrate against the second substrate and then removing the first substrate. An additional structure is then produced on the second substrate. This additional structure includes volumes of material placed in correspondence with some of the volumes of differentiated material of the defined pattern. The electronic components thus produced may have a suitable configuration in accordance with technological or geometrical constraints. In a preferred method, a selective treatment is applied to the transferred part of the initial structure, so as to make a distinction between the volumes of differentiated material of the pattern.
REFERENCES:
patent: 4317125 (1982-02-01), Hughes et al.
patent: 4968628 (1990-11-01), Delgado et al.
patent: 5004705 (1991-04-01), Blackstone
patent: 5244817 (1993-09-01), Hawkins et al.
patent: 5369050 (1994-11-01), Kawai
patent: 5436173 (1995-07-01), Houston
patent: 5506163 (1996-04-01), Moriya
patent: 6066513 (2000-05-01), Pogge et al.
patent: 6110806 (2000-08-01), Pogge
patent: 6329265 (2001-12-01), Miyawaki et al.
patent: 6335224 (2002-01-01), Peterson et al.
patent: 6392144 (2002-05-01), Filter et al.
patent: 6701779 (2004-03-01), Volant et al.
patent: 6709949 (2004-03-01), Hubner
patent: 2001/0032987 (2001-10-01), Narui et al.
patent: WO 00/36383 (2000-06-01), None
Van Zant MicroChip Fabrication, 4th ed. McGraw Hill 2000. p. 559.
XP 000167661 on Oct. 3, 1989, by R. P. Zingg et al., Dual-Gate SOI CMOS Technology by Local Overgrowth (LOG), Proceedings of the Annual SOS/SOI Technology Conference.
Coronel Philippe
Leverd Francois
Skotnicki Thomas
Bongini Stephen
Fleit Kain Gibbons Gutman Bongini & Bianco P.L.
Ghyka Alexander
Jorgenson Lisa K.
STMicroelectronics S.A.
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