Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2002-11-19
2004-04-27
Pert, Evan (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S765010, C438S017000
Reexamination Certificate
active
06727718
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a surface-mount package, a printed circuit board having the package mounted thereon, and a method of inspecting the assembled printed circuit board and package, and more particularly, to a ball grid array package, a printed circuit board having the ball grid array package mounted thereon, and a method of inspecting the assembled printed circuit board and ball grid array package.
2. Description of the Related Art
In recent years, a ball grid array (hereinafter referred to as “BGA”) package, which is a key device in high-density mounting technology, has been applied to communications devices such as a portable telephone. Moreover, the BGA package is now starting to be applied to trunk communications devices. It is expected that the BGA package continues to be applied to a wider range of applications as an LSI (Large-Scale Integration) package, to replace the large-sized QFP (Quad Flat Package) with a fine lead pitch.
FIGS.
18
(A) and
18
(B) schematically show external configurations of a conventional BGA package. FIG.
18
(A) is a side view, while FIG.
18
(B) is a bottom view. The BGA package
200
has a package body
201
in which semiconductor chips are laminated, and the package body
201
has a bottom thereof formed with a plurality of footprints (pads)
202
on which respective ball-shaped solder bumps
203
are formed on the respective footprints
202
.
The BGA package
200
is mounted on a printed circuit board by soldering the solder bumps
203
onto the printed circuit board.
FIG. 19
shows the BGA package
200
mounted on the printed circuit board. The printed circuit board
204
is formed with footprints
205
thereon to which the respective solder bumps
203
are soldered. In order to solder the BGA package
200
onto the printed circuit board
204
, similarly to an operation for soldering typical surface-mount components, solder paste
206
is applied onto the respective footprints
205
by a screen printing process, and then the BGA package
200
is placed on the solder paste
206
, followed by melting the solder paste
206
and the solder bumps
203
by the use of a heating apparatus.
In general, if the printed circuit board
204
having the BGA package
200
mounted thereon receives a shock e.g. when it is carelessly dropped while being handled, the printed circuit board
204
is distorted, which affects solder joints on the BGA package
200
. Each terminal of the BGA package
200
has a larger solder joint area than that of conventional components having leads connected thereto, so that soldered joint strength between the solder bumps
203
and the footprints
205
is relatively high. This prevents the solder bumps
203
and the footprints
205
from breaking away from each other.
However, if joint strength between the package body
201
of the BGA package
200
and the respective footprints
202
or between a substrate surface of the printed circuit board
204
and the respective footprints
205
is low, forces generated by any distortion of the printed circuit board
204
are likely to crack some of the footprints
202
,
205
or cause the same to break away from the package body
201
or the printed circuit board
204
. Thus, when the printed circuit board
204
receives a shock, the solder bumps
203
in the outermost rows and columns are especially prone to such cracking and breakaway since vibrations, warping, expansion, and/or contraction, have the maximum effect at the edge or peripheral portions of the printed circuit board
204
.
To overcome this problem, a method is conventionally employed in which a reinforcing adhesive
207
is applied to the outermost solder bumps
203
and its vicinity, as shown in
FIG. 19
, so as to securely join the outermost solder bumps
203
, the package body
201
, and the printed circuit board
204
to each other.
However, this method increases the number of manufacturing steps, resulting in degraded working efficiency. Moreover, when the BGA package
200
is defective, it is required to discard the printed circuit board
204
together with the package
200
rather than simply replace the package
200
with a new one. This results in the waste of materials as well as an increase in manufacturing costs.
Further, since it is impossible to judge by visual inspection whether any of the solder joints on the BGA package
200
is defective, the inspection of electrical connections of the solder joints is conventionally performed at an electronic testing stage of the manufacturing process. However, the conventional electronic test cannot detect either a breakaway or a crack of the footprint
202
or
205
unless there is a disconnection in any pattern connected to the solder bumps
203
.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide an electronic component package and a printed circuit board which are capable of improving working efficiency in mounting the electronic component package on the printed circuit board, and at the same time preventing a breakaway of footprints formed on the electronic component package for circuit connection.
A second object of the invention is to provide a method of inspecting the printed circuit board, which is capable of detecting a defect, such as a breakaway and a crack, of footprints.
To accomplish the first object, according to a first aspect of the invention, there is provided an electronic component package of ball grid array type. The electronic component package is characterized by comprising a plurality of circuit-connecting bumps formed in a predetermined area, and at least one reinforcing bump formed in an area located outward of the predetermined area, in a manner such that the at least one reinforcing bump is connectable to at least one reinforcing pattern formed on a printed circuit board.
To accomplish the second object, according to a second aspect of the invention, there is provided a method of inspecting a printed circuit board having an electronic component package mounted thereon. This method is characterized by comprising the steps of forming a bridge circuit between reinforcing bumps formed on the electronic component package, and reinforcing footprints formed on the printed circuit board in a manner such that the reinforcing bumps are connected to the reinforcing footprints, and detecting a change in a resistance value of the bridge circuit to thereby detect a defect of the printed circuit board.
The above and other objects, features and advantages of the present invention will become apparent from the following description when taken in conjunction with the accompanying drawings which illustrate preferred embodiments of the present invention by way of example.
REFERENCES:
patent: 3335327 (1967-08-01), Damon et al.
patent: 3353139 (1967-11-01), Ribbelink
patent: 3871014 (1975-03-01), King et al.
patent: 4604644 (1986-08-01), Beckham et al.
patent: 5381307 (1995-01-01), Hertz et al.
patent: 5386342 (1995-01-01), Rostoker
patent: RE35119 (1995-12-01), Blonder et al.
patent: 5539153 (1996-07-01), Schwiebert et al.
patent: 5598036 (1997-01-01), Ho
patent: 5748450 (1998-05-01), Kim et al.
patent: 5770891 (1998-06-01), Frankeny et al.
patent: 5847936 (1998-12-01), Forehand et al.
patent: 5854534 (1998-12-01), Beilin et al.
patent: 5901046 (1999-05-01), Ohta et al.
patent: 5907187 (1999-05-01), Koiwa et al.
patent: 5982033 (1999-11-01), Ohsawa et al.
patent: 6046499 (2000-04-01), Yano et al.
patent: 6111322 (2000-08-01), Ando et al.
patent: 6222277 (2001-04-01), Downes
patent: 6346679 (2002-02-01), Nakamura
patent: 6395991 (2002-05-01), Dockerty et al.
patent: 6426468 (2002-07-01), Utsunomiya et al.
patent: 6465743 (2002-10-01), Owens
Abstract of Japanese Publication No. 7-050475.
Abstract of Japanese Publication No. 8-153819.
Abstract of Japanese Publication No. 8-316268.
Arase Fumio
Ichihara Yasuhiro
Iimura Hiroshi
Kogure Seiji
Fujistu Limited
Pert Evan
Westerman Hattori Daniels & Adrian LLP
LandOfFree
Electronic component package, printed circuit board, and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Electronic component package, printed circuit board, and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electronic component package, printed circuit board, and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3198654