Electronic component having a semiconductor chip

Details Electronic component having a semiconductor chip Electronic component having a semiconductor chip

2001-05-07

2003-11-25

Zarabian, Amir (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S620000, C257S760000, C438S462000, C438S626000

Reexamination Certificate

active

06653732

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to an electronic component having a semiconductor chip comprising a multi-layered coating that includes at least one interconnect layer, one insulation layer, and one planarization layer.
Planarization layers manifest problems adhering to insulation and/or interconnect layers, particularly in view of that fact that their thermal coefficient of expansion is not suited to the expansion behavior of the insulation layers and/or interconnect layers at all processing temperatures that arise in the process of manufacturing the electronic component. The danger of a detachment of the planarization layer increases in correspondence to the distance from the thermo-mechanical neutral point of the semiconductor chip, which is located in the geometric center of the surface of the active semiconductor chip given a symmetrical construction of the semiconductor structures, the structured insulation layers and the structured interconnect layers. Given an asymmetrical construction of a multi-layer coating of a semiconductor chip, the thermo-mechanical neutral point can be offset from the geometric center of the semiconductor chip. Despite this offset, the thermo-mechanical neutral point of a semiconductor chip is located in the vicinity of the geometric center of a semiconductor chip and thus in the center region. Thus, the problem regions with respect to the adhesion of the planarization layer to insulation layers are situated in the corner regions of a semiconductor chip.
SUMMARY OF THE INVENTION
It is the object of the invention to prevent the disengagement or displacement of a planarization layer from a semiconductor having a multi-layer coating.
This object is achieved with the subject matter of the independent claim. Additional advantageous developments of the invention derive from the subclaims.
According to the invention, the planarization layer comprises a glass layer having embedded adhesion regions which provide adhesion surfaces to neighboring insulation layers. These embedded adhesion regions have the advantage that they can be inserted in all problem zones of the planarization layer. Since the adhesion surfaces of the adhesion regions are fixed in relation to the adjacent insulation layers, the glass layer is prevented from sliding and lifting off at these adhesion regions, and the glass layer is fixed between the adhesion regions. To this end, the adhesion regions are applied to the semiconductor chip having a multi-layer coating prior to application of the glass layer.
In an embodiment of the invention, the glass layer consists of a glass compound that is thrown or spun on and polished on the surface which is averted from the semiconductor chip for leveling purposes. When it is thrown or spun on, the glass compound initially covers not only the adhesion regions with their adhesion surfaces for adjacent insulation layers, but also covers unevennesses of the multi-layer semiconductor chip as well as through-contacts to underlying interconnects. Polishing the surface of the glass layer erodes it sufficiently to produce a plane that comprises glass layer regions, through-contact regions, and adhesion regions, so that additional insulation layers, interconnect layers and through-contacts can be built on this plane with a high degree of precision, a completely planar surface being available again for such further processing of the semiconductor chip.
In another development of the invention, the adhesion regions consist of a metal coating. Metal coatings on insulation layers on semiconductor chips have the advantage of adhering extremely durably, so that such a metal coating on the insulation layer of a multi-layer coating of a semiconductor chip fundamentally represents an obstacle to the sliding of the glass layer of the planarization layer.
When the ultimate layer structure subsequent to the planarization layer begins with an additional insulation layer, the adhesion areas are sandwiched between lower and upper insulation layers, to which metal coatings adhere particularly well, so that the region of the planarization layer which is occupied by the glass layer is prevented from sliding or disengaging from the underlying bottom insulation layer and/or the overlying top insulation layer.
In another embodiment of the invention, the adhesion regions of the planarization layer are denser in corner regions of the semiconductor chip than in the center region of the semiconductor chip. By extension, this advantageous embodiment of the invention may provide that no adhesion regions be arranged in the center region, and that the arrangement of adhesion regions be concentrated in the corner regions, especially since the corner regions in a semiconductor chip are located furthest from the thermo-mechanical neutral point of the semiconductor chip.
The adhesion regions can have a variety of shapes. In one embodiment of the invention, the planarization layer of the semiconductor chip comprises angular strips as the adhesion regions in corner regions of the semiconductor chip. The angles can be rectangular, with the legs of the angular strips growing shorter as the strips approach the center of the semiconductor chip. The stagger, i.e. the mutual spacing between the angular strips, can also be varied so that the spacing between the angular strips increases as they approach the center. The angular strips are interrupted at the locations at which through-contacts are required for contacting through to the bottom interconnect layers.
Another embodiment of the invention provides that the planarization layer of the semiconductor chip comprise adhesion regions with rounded contours. Rounded contours represent adhesion regions that do not comprise corners, vertices or indentations, so that microtear formation is not induced in the surrounding glass layer given cyclic thermal stress. For this reason, round, i.e. circular, adhesion regions are advantageous.
The adhesion regions are produced from materials whose adhesivity on insulation layers in semiconductor technology has been proven effective. In particular, in one embodiment of the invention the adhesion regions consist of an aluminum alloy coating. Aluminum alloys having small proportions of copper and/or silicon have proven effective and adhere permanently to the insulation layers, so that in an electronic component wherein adhesion regions consisting of aluminum alloys are embedded in the planarization layer, these regions can effectively adhere both to the underlying bottom insulation layer and to the subsequent overlying top insulation layer, and can thus prevent the material of the planarization layer from lifting or sliding off at the critical adhesion locations far from the thermo-mechanical neutral point of the semiconductor chip.
Since copper alloys are being used with increasing frequency in semiconductor technology for the interconnect layers, it is expedient to produce the adhesion regions in semiconductor chips having copper interconnect layers from copper alloys, in order to remain compatible with the respective process technologies.
A further object of the present invention is to optimize and test the geometry of the adhesion regions, their position on the chip, and the materials for the adhesion regions.
This object is achieved by an electronic component having a test structure on a semiconductor chip, which structure comprises a multi-layer coating including at least one interconnect layer, one bottom insulation layer, one top insulation layer, and one intermediate planarization layer with embedded adhesion regions, and which additionally comprises at least one test through-contact in the corner regions of its planarization layer, which extends through the planarization layer and is connected above and below the planarization layer to measuring interconnects.
The test through-contact has a microscopic diameter, given which it is possible to detect minimal displacements of the planarization layer. In this context, the term “microscopic” refers to dimensions that ar

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