Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
1999-07-08
2003-04-29
Eckert, II, George C. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S786000
Reexamination Certificate
active
06555913
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electronic component and a production method thereof. More specifically, the present invention relates to an electronic component such as a surface mount type inductor or strip line component, or other similar component, which is to be mounted on the surface of a pattern of a printed circuit board, and a production method thereof.
2. Description of the Related Art
A method of manufacturing a surface mount type inductor having a high Q value includes forming a coil conductive pattern on a ceramic mother substrate by a screen printing process with a large coil conductive pattern film thickness (large cross-sectional area) for having a small coil conductive pattern direct current resistance value (conductor loss) is commonly known. However, according to this screen printing method, the size of the coil conductive pattern is extremely irregular in terms of the accuracy. In addition, the deviation of the inductance values is large and it is difficult to have a narrow conductor width for the coil conductor.
On the other hand, as a method of manufacturing an inductor with a small inductance value deviation, a method of forming a metal film on a mother substrate via sputtering, deposition, or the like, and forming a coil conductor pattern using photolithography technology is commonly known. However, according to this method, it is difficult to have a thick coil conductor pattern thickness compared with the screen printing method, and thus, it is difficult to produce an inductor with a high Q value.
Then, as a method of producing an inductor with a high Q value and a small inductance value deviation, a method of forming a coil conductor pattern including a combination of thick film printing and photolithography technology, using a photosensitive conductive paste, and a method of forming a coil conductor pattern with a thick film and a high size accuracy via a method referred to as a semi-additive process have been proposed (see, for example, the Official Gazettes of Japanese Unexamined Patent Publication Nos. 8-316080 and 945570).
However, due to a high production cost caused by a large number of manufacturing and processing steps required by the semi-additive process, a method of using a photosensitive conductive paste is preferable. However, in order to obtain a small size inductor having a large inductance value, a very small size coil conductor pattern must be formed within a limited coil conductor forming area. Therefore, even in the case of using a photosensitive conductive paste in the conventional method, a problem occurs in that the line width of the coil conductor pattern becomes small so as to have a large conductor loss, and thus, the Q value is lowered. Moreover, since the limit of the resolution of a photosensitive conductive paste in the thickness direction has an aspect ratio of 1 (after development), it is difficult to have a thicker photosensitive conductive paste film. The aspect ratio of a coil conductor pattern is defined as the ratio of the thickness to the pattern width of a coil conductor pattern.
SUMMARY OF THE INVENTION
To overcome the problems described above, preferred embodiments of the present invention provide a very small size electronic component having a small direct current resistance value in a conductor pattern and an extremely accurate conductor pattern size, and a production method thereof.
According to one preferred embodiment of the present invention which achieves the advantageous results described in the preceding paragraph, an electronic component includes a conductor pattern having a lower conductor pattern layer disposed on an insulating substrate and an upper conductor pattern layer laminated on the lower conductor pattern layer, wherein a ratio of the conductor pattern thickness and the pattern width is equal to or greater than about 1.
Since the conductor pattern includes the lower conductor pattern layer and the upper conductor pattern layer, the cross-sectional area thereof is preferably substantially equal to the sum of the cross-sectional area of the lower conductor pattern layer and the cross-sectional area of the upper conductor pattern layer. Accordingly, the cross-sectional area of the conductor pattern can be large, and thus, the direct current resistance value of the conductor pattern can be reduced. Furthermore, by having a coil conductor pattern preferably having a spiral shape as the conductor pattern, an inductor having a high Q value and a large inductance value is achieved. Moreover, since the aspect ratio defined as the ratio of the conductor pattern thickness to the pattern width is equal to or greater than about 1, the pattern width size of the conductor pattern can be minimized, and thus, the area on the insulating substrate occupied by the conductor pattern is greatly reduced without increasing the direct current resistance value of the conductor pattern.
Moreover, another preferred embodiment of the present invention provides a method of manufacturing an electronic component including a conductor pattern having a lower conductor pattern layer disposed on an insulating substrate and an upper conductor pattern layer laminated on the lower conductor pattern layer, the method including the steps of forming the lower conductor pattern layer on the insulting substrate, applying an insulating material on the insulating substrate as a film so as to cover the lower conductor pattern layer and eliminating the insulating material until at least the upper surface of the lower conductor pattern layer is exposed so as to form an inter-line insulating layer, and forming the upper conductor pattern layer on the lower conductor pattern layer.
Furthermore, according to another preferred embodiment of the present invention, a method of manufacturing an electronic component including a conductor pattern having a lower conductor pattern layer disposed on an insulating substrate and an upper conductor pattern layer laminated on the lower conductor pattern layer, the method including the steps of applying a photosensitive conductive material on the insulating substrate as a film and exposing and developing the photosensitive conductive material through a photo mask for forming the lower conductor pattern layer, applying an insulating material on the insulating substrate as a film so as to cover the lower conductor pattern layer and eliminating the insulating material until at least the upper surface of the lower conductor pattern layer is exposed so as to form an inter-line insulating layer, and applying a photosensitive conductive material on the inter-line insulating layer and the lower conductor pattern layer as a film and exposing and developing the photosensitive conductive material through a photo mask for forming the upper conductor pattern layer on the lower conductor pattern layer.
According to the above-mentioned methods, a lower conductor pattern layer and an upper conductor pattern layer of a conductor pattern can be formed easily. Moreover, the resulting conductor pattern has a high aspect ratio which is higher than the resolution limit of the conductive material in the depth direction.
Furthermore, by repeating the steps of forming an inter-layer insulating layer having via holes on the inter-line insulating layer and the conductor pattern, forming a lower conductor pattern layer, forming an inter-line insulating layer and forming an upper conductor pattern layer subsequently, an electronic component having a multi-layer structure in which a plurality of the conductor patterns are provided with an inter-layer insulating layer provided therebetween is provided.
To achieve the advantages described in the preceding paragraph, a method of manufacturing an electronic component according to the present invention includes the steps of applying an insulating material on an insulating substrate as a film and eliminating a specific component of the insulating material so as to form an inter-line insulating layer having a pattern groove and filli
Amaya Keishiro
Kawaguchi Masahiko
Sasaki Toshiya
Tamezawa Eita
Uchiyama Kazuyoshi
Eckert II George C.
Keating & Bennett LLP
Murata Manufacturing Co. Ltd.
Peralta Ginette
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