Electronic component device, and main board for circuit boards

Details Electronic component device, and main board for circuit boards Electronic component device, and main board for circuit boards

2000-05-11

2001-11-27

Picard, Leo P. (Department: 2841)

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

C361S760000, C361S764000, C174S255000, C174S262000, C228S180220, C029S846000, C029S832000

Reexamination Certificate

active

06324068

ABSTRACT:

TECHNICAL FIELD
The present invention relates to an electronic component device having a circuit board on which are mounted electronic components such as IC chips and on which are formed electrode patterns for external connections, and to a method for manufacturing the same as well as to a main board for circuit boards for use in manufacturing the electronic component device.
BACKGROUND ART
With reduced dimensions and increased density of flip chip semiconductor packages, a flip chip bonding has been developed which allows bare chips to be mounted directly on a substrate. Moreover, a hand-held equipment such as a camera-integrated VTR or a cellular phone has recently appeared one after another which is mounted with small-sized packages, so-called CSPs (chip size/scale packages) which have substantially the same dimensions as those of the bare chips. In such circumstances, a demand of market for the CSPs is significantly increased, inducing a recent rapid development of the CSPs.
A main board for circuit boards is used for the manufacture of the flip chip semiconductor packages in the form of the CSPs. The main board consists of a plurality of circuit boards which are integrally arranged and formed. Both side surfaces of each circuit board are formed with electrode pads (hereinafter referred to as bonding pads) for mounting IC chips thereon and with electrode pads for external connections which are electrically connected via through-holes to the bonding pads. After the mounting of the IC chips thereon, the main board is separated into the plurality of circuit boards.
Referring now to FIGS.
10
(A)-
10
(F), description is made for a process for forming a conventional aggregated circuit board.
FIGS.
10
(A)-
10
(F) are process diagrams for explaining the board formation process of the main board for circuit boards.
Prior to the formation of the main board, an insulating base material
101
is first prepared which is made of ceramics or resin and in which both side surfaces are clad with copper films
102
(FIG.
10
(A)).
A through-hole
103
is then formed in this copper-clad base material
101
(FIG.
10
(B)).
By means of electroless copper plating or electrolytic copper plating, a copper plating layer
104
is formed on the both side surfaces of the base material
101
having the through-hole
103
formed therein (FIG.
10
(C)). The copper plating layer
104
is formed on the copper films
102
and on the side wall of the through-hole
103
. This copper plating layer
104
allows the both side surfaces of the base material
101
to electrically conduct to each other.
A filler material
105
such as resin is then filled into the through-hole
103
(FIG.
10
(D)).
The copper plating layer
104
is further laminated with plating resists which are in sequence exposed to light and developed to form a pattern mask (not shown). Afterward the copper plating layer
104
is subjected via this pattern mask to a pattern etching using an etching liquid or the like. As a result of this pattern etching, a plurality of electrodes (bonding patterns)
3
for IC connections are arranged on the top surface side of the main board
100
, with the formation of electrodes
4
for external connections in the form of pad electrodes arranged on the bottom surface side in a matrix manner (FIG.
10
(E)).
Solder resist processing is then carried out to form a solder resist film
106
on the bottom surface side of the main board
100
(FIG.
10
(F)). This solder resist film
106
has openings which allow the electrodes
3
for IC connections and the electrodes
4
for external connections to be partially exposed. Portions of the electrodes
3
for IC connections and of the electrodes
4
exposed in the openings form respectively bonding pads
3
a
which are solderable regions and electrode pads
4
a
for external connections. By virtue of the formation of this solder resist film
106
, the surface of the main board
100
becomes flattened. Furthermore, a gold plating (not shown) is usually provided on the surfaces of the bonding pad
3
a
and the electrode pad
4
a.
Thus, there is finished the main board
100
having a multiplicity of solderable regions of the same geometry arranged on its surface in a matrix manner.
Referring is then made to FIGS.
11
(A) to
12
(B) to schematically describe a method for manufacturing a BGA (ball grid array) of a flip chip having solder ball electrodes formed on its circuit board, the method being an example of a conventional method for manufacturing a CSP flip chip semiconductor package.
In FIGS.
11
(A) to
11
(C) and in FIGS.
12
(A) and
12
(B), top plan views are on the right side of the diagrams and sectional views taken along respective cutting lines of the top plan views are on the left side of the top plan views.
It is to be noted that FIGS.
11
(A) to
12
(B) illustrate examples in which four circuit boards
1
are formed therefrom for convenience.
The conventional semiconductor package manufacturing process includes a main board formation process (FIG.
11
(A)), an IC chip mounting process (FIG.
11
(B)), a resin sealing process (FIG.
11
(C)), a reference member attachment and electrode formation process (FIG.
12
(A)) and a dicing process (FIG.
12
(B)).
For the manufacture of the BGA, the main board
100
formed by the above main board formation process (FIG.
11
(A)) is prepared.
Although in FIG.
11
(A) the electrodes
3
for IC connections and the electrodes
4
for external connections are diagrammatically shown as raised portions, the electrodes
3
for IC connections and the electrodes
4
for external connections are actually in the form of recessed portions as set forth above.
Then, prior to the mounting of the IC chips, solder bumps
5
are formed on top of pad electrode faces of an IC wafer (not shown). Known as the method for forming these solder bumps
5
are, for example, a stud bump method, a ball bump method and a plating bump method, etc. Among these methods, the plating bump method is effective for the downsizing of the IC chips since it allows the bumps to be formed in narrow arrays between the pad electrodes.
The IC wafer having solder bumps formed thereon is then cut into predetermined chip sizes while being adhered to an adhesive tape, to form IC chips
6
. In the cutting, use is a device such as a dicing saw to cut the IC wafer in X and Y directions in a full-cut mode. Afterward, the IC chips
6
on the adhesive tape are separated into unitary components.
Then, in the IC chip mounting process, as shown in FIG.
11
(B), flip chips are mounted one by one on the associated circuit boards of the main board
100
. For the flip chip mounting, flux (not shown) is first applied to any predetermined positions on the electrodes
3
for IC connections (see FIG.
11
(A)) formed on the solder bumps
5
or on the top surface side of the main board
100
. Afterward, the IC chips
6
are placed one by one for each circuit board
1
on the main board
100
. For the placement, the surface side of the IC chips
6
having the solder bumps
5
formed thereon is made to confront the top surface side of the main board
100
, with the solder bumps
5
being positioned on the electrodes
3
for IC connections. Subsequently, solder reflow is carried out to electrically connect the electrodes
3
for IC connections to these IC chips
6
. Thus, the IC chips
6
are mounted on the main board
100
.
Then, in the sealing process, use is a thermosetting sealing resin
7
to perform side potting over a plurality of adjacent IC chips
6
, to thereby integrally resin seal the plurality of IC chips
6
. By virtue of this, as shown in FIG.
11
(C), the IC chips
6
are fixed on the individual circuit boards
1
of the main circuit board
100
with facedown in a sealed manner.
Then in the reference member attachment process, the top surfaces of the IC chips
6
mounted on the main board
100
are adhesively attached on the reference member
8
by means of fixing means such as an adhesive agent or an adhesive tape.
Then, in the electrode formation process, solder balls are f

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