Electronic circuit with processing units coupled via a...

Details Electronic circuit with processing units coupled via a... Electronic circuit with processing units coupled via a...

2004-08-10

2011-11-29

Ton, Dang (Department: 2475)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C710S316000

Reexamination Certificate

active

08068508

ABSTRACT:
A two-way network interface is provided for both sending transmission messages and receiving reception messages between a pair of processors through a network. The network interface uses transmission messages to transmit both data and information representing respective amounts of unreported buffer space R for receiving data items from reception messages in a buffer storage circuit. The network interface holds up transmission until a number A of data items, that a particular one of the data processing circuits has made available for transmission in the message and for which buffer space is available across the network, exceeds a threshold. However the threshold is lowered, or the transmission message is transmitted before the threshold is exceeded in response to an increase in the amount R of unreported available buffer space in the buffer storage circuit for the particular one of the processing circuits.

REFERENCES:
patent: 5367523 (1994-11-01), Chang et al.
patent: 5453982 (1995-09-01), Pennington et al.
patent: 6240095 (2001-05-01), Good et al.
patent: 6247077 (2001-06-01), Muller et al.
patent: 6289386 (2001-09-01), Vangemert
patent: 6337865 (2002-01-01), Seto et al.
patent: 6426943 (2002-07-01), Spinney et al.
patent: 6460080 (2002-10-01), Shah et al.
patent: 6594701 (2003-07-01), Forin
patent: 6657962 (2003-12-01), Barri et al.
patent: 2004/0202155 (2004-10-01), Natarajan et al.
patent: 2010/0046370 (2010-02-01), Ghose et al.
patent: 0041365 (2000-07-01), None
patent: WO 00/67131 (2000-11-01), None
Bhoedjang, R. A. F. et al: Efficient Multicast on Myrinet Using Link-Level Flow Control IEEE Comput. Soc. Aug. 1998, pp. 381-390, XP010298402.
Liu J. et al: High Performance RDMA-Based MPI Implementation Over Infiniband ACM, vol. Conf. 17, Jun. 2003, pp. 295-304, XP001198482.
Verma M. et al: Pupa: A Low-Latency Communication System for Fast Ethernet, IPDPS Apr. 1998, pp. 1-13, XP002305195.
Roger Zimmermann, et al: A Multi-Threshold Onling Smoothing Technique for Variable Rate Multimedia Streams.
Dah Ming Chiu, et al: A Congestion Control Algorithm for Tree-Based Reliable Multicast Portocols, SMLI TR-2001-97, Jun. 2001.
Dr, Syed Ljlil Ali Shah, Bringing Comprehensive Quality of Service Capabilities to Next-Generation Networks, pp. 1-19.
Mellanox Technologies Inc: Introduction to Infiniband, No. WPO010800120.
Nazy Alborx, et al: Implementation of VirtualClock Scheduling Algorithm in OPNET.

Affiliated with

Also associated with

Rating

Electronic circuit with processing units coupled via a... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Electronic circuit with processing units coupled via a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electronic circuit with processing units coupled via a... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4279891