Electronic circuit with clock generating circuit

Details Electronic circuit with clock generating circuit Electronic circuit with clock generating circuit

2000-11-09

2003-09-09

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S091000, C327S327000, C327S043000

Reexamination Certificate

active

06617904

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention relates to an electronic circuit with a clock signal generator circuit.
U.S. Pat. No. 5,341,031 describes a clock generator circuit. This clock generator circuit divides an input clock signal. The input clock signal clocks a latch that samples the divided signal once for every period of the input clock signal. Thus, a derived clock signal is produced that has a well-defined phase relation with respect to the input clock signal. However, in this circuit works only for derived clock signal that have a frequency equal to or less than half the frequency of the input clock signal.
European patent application No. 785624 also describes a clock generator circuit. In this clock generator circuit the input clock signal is processed to generate a derived clock signal, for example by clock windowing. This processing causes delays, which give the derived clock signal an ill-defined phase relation with respect to the input clock signal. The circuit of EP 785624 overcomes this problem using a resynchronized version of the derived clock signal.
To perform resynchronization, the circuit of EP 785624 contains two resynchronization circuits, a first one constituted by two D-latch stages and a second one constituted by a single D-latch stage. The resynchronization circuits latch the derived clock signal at points in time that are defined by the input clock signal. The resynchronization circuits produce two signals that are synchronous with the input clock signal, but out of phase with respect to one another by a semi-period of the input clock signal. An EXOR circuit forms a logical EXOR of these two signals. The EXOR circuit produces output pulses when the logic level of the derived clock signal changes. The duration of the output pulses is half a period of the input clock signal, that is, the same duration as the duration of pulses of the input clock signal. The derived clock signal has half the frequency of the input clock signal, and so the output of the EXOR has the same frequency as the input clock signal.
It is desirable to generate any kind of resynchronized derived signals with a minimum pulse duration that is the same as that of the input clock signal. However, the technique of EP 785624 applies only to specific signals that can be generated with an EXOR of two phase-shifted signals.
SUMMARY OF THE INVENTION
It is an object of the invention to provide for an electronic circuit that is able to generate arbitrary derived clock signals with a minimum pulse duration that is equal to that of the input clock signal.
The electronic circuit according to the invention is described in claim 1. According to the invention, the clock generator circuit uses a dual edge triggered flip-flop to sample the derived clock signal. Dual edge triggered flip-flops are known per se, for example from U.S. Pat. No. 5,793,236. The dual edge triggered flip-flop in the circuit according to the invention samples the derived clock signal both at the rising and the falling edges of the input clock signal. Thus, pulses of the derived clock signal with a duration down to half a period of the input clock signal are sampled correctly.
As a result, the sampling circuits works properly when the frequency of the derived clock signal is equal to that of the input clock signal.
An embodiment of the electronic circuit according to the invention contains a plurality of dual edge triggered flip-flops each for producing a respective sampled derived clock signal. These dual edge triggered flip-flops receive the input clock in common. As a result, all the sampled derived clock signals are synchronized. At least one of the derived clock signals may have the same frequency as the input clock signal. Thus, the sampled version of that derived clock signal will have the same delay with respect to the input clock signal as the other sampled versions of derived clock signals (a delay due to the operation dual edge triggered flip-flop). This sampled version can be used instead of the input clock signal to control processing circuits in combination with the other sampled versions of derived clock signals. Preferably, the dual edge triggered flip-flops are located close to the processing circuits that use these signal (i.e. closer than to the circuit that derives the clock signals), so as to eliminate mutually different propagation delays.


REFERENCES:
patent: 4980577 (1990-12-01), Baxter
patent: 5341031 (1994-08-01), Kinoshita et al.
patent: 5532633 (1996-07-01), Kawai
patent: 5793236 (1998-08-01), Kosco
patent: 6072336 (2000-06-01), Yamaguchi
patent: 6271702 (2001-08-01), Stansell
patent: 0785624 (1997-07-01), None

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