Electronic circuit with capacitively enhanced switching

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307494, 307263, 307270, 307443, H03K 19086, H03K 512, H03K 301, G06G 712

Patent

active

050878379

ABSTRACT:
A circuit formed with an input stage (20) and an output stage (22 or 28) uses capacitively enhanced switching to improve switching speed without significantly raising steady-state current utilization. The output stage contains a pair of amplifiers (A1and A2) that respond to complementary signals (V.sub.M1 and V.sub.M2) produced by the input stage. The amplifiers are coupled to a pair of corresponding nodes (N1 and N2). A third amplifier (A3) in the output stage has a control electrode coupled to one of the nodes, a flow electrode coupled to the other node, and another flow electrode coupled to a further node (N3). A current supply (24) provides current at the further node. A charge/discharge element (CD1) produces a capacitive-type charge/discharge action between the further node and a source of a reference voltage (V.sub.R1). The output stage may also include a fourth amplifier (A4), another current supply (26), and another such charge/discharge element (CD2) arranged in a complementary manner to the three preceding components.

REFERENCES:
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patent: 4642482 (1987-02-01), Kasperkovitz et al.
patent: 4678942 (1987-07-01), Kanai et al.
patent: 4680480 (1987-07-01), Hopta
patent: 4920284 (1990-04-01), Denda
Toh et al., "A 23 ps/2.1 mW ECL Gate", 1989 IEEE Int'l. Solid-State Cirs. Conf., Dig. Tech. Paps., 17 Feb. 1989, pp. 224-225.
Coy et al., "A 13,000 Gate 3 Layer Metal Bipolar Gate Array", Procs. IEEE 1988 Custom ICs Conf., 16-19 May 1988, pp. 20.1.1-20.1.3.
Ostaszewski et al., "Sea-of-Cells, ECL Arrays Come of Age", VLSI System Design, Nov. 1988, pp. 18-19, 22, 24, 28 and 32.

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