Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating
Patent
1996-08-15
1998-03-31
Callahan, Timothy P.
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Clock or pulse waveform generating
327304, G06F 104
Patent
active
057342857
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
This invention relates to electronic circuits. More specifically, this invention relates to the reduction of power consumption in electronic circuits.
BACKGROUND ART
An electronic circuit consumes power in various ways. In particular, power is consumed when input signals to elements of the circuit change,state. This power consumption occurs as a result of the charging and discharging of parasitic capacitances associated with the inputs to the circuit elements. Power is not dissipated in the parasitic capacitances themselves but, instead, in the output resistances of earlier circuit elements that furnish the input signals. In modern synchronous integrated circuits ("ICs"), a large portion of the power consumption occurs in clock drivers that provide clock signals to the functional circuit elements.
Referring to the drawings, FIG. 1 illustrates a conventional synchronous CMOS IC useful in understanding clock-driver power consumption. The circuit in FIG. 1 contains a clock driver 10 that furnishes a circuit clock signal CKD on a circuit clock line 12 in response to an input clock signal CKI. Clock driver 10 consists of a group of CMOS inverters 10D connected in parallel. Each inverter 10D is formed with a pair of complementary insulated-gate field-effect transistors ("FETs") QN and QP connected in series between circuit ground and a source of a high supply voltage V.sub.HH.
Clock signal CKD is provided by way of a clock net to the clock inputs of function elements 14F in function circuitry 14. The clock net consists of the lines that branch out from clock line 12 and go to function elements 14F. A parasitic capacitance is associated with the clock input section of each element 14F. The lines that form the clock net also have their own parasitic capacitances.
Function elements 14F are built in proximity to, or contain components connected to, at least one low-impedance source of fixed reference voltage, typically earth or circuit ground potential. The lines that form the clock net are similarly situated in proximity to at least one low-impedance source of fixed reference voltage. To a good approximation, the parasitic capacitances of the clock net lines and the clock inputs to elements 14F can be represented by a single capacitor CP1 connected between clock line 12 and the ground-potential source.
Typically, (a) the clock input resistance of each function element 14F is very high, (b) the propagation delay from driver 10 to the most remote of elements 14F is small compared to clock-frequency period, and (c) the clock-net lines have low resistance and inductance. To a reasonable approximation, the load that clock CKD presents to driver 10 can likewise be represented by capacitor CP1 since it is also connected between the output of driver 10 and the ground-potential source.
Input clock signal CKI switches between a low voltage level, typically ground reference, and a high voltage level, typically V.sub.HH, at an input clock frequency f.sub.CKI. During a full clock cycle in which input clock CKI goes from one level to the other level and then back to the first, driver 10 expends an energy equal to C.sub.P1 V.sub.HH.sup.2, where C.sub.P1 is the value of parasitic capacitance CP1. Half of this energy is dissipated as heat by the QP channel resistances when current flows from the V.sub.HH supply through FETs QP to charge capacitance CP1 during one half of the clock cycle. The remaining half of energy C.sub.P1 V.sub.HH.sup.2 is dissipated as heat by the QN channel resistances when current flows through FETs QN to discharge capacitance CP1 during the other half of the clock cycle.
The number of functional elements 14F in some modern synchronous ICs is very high. As a consequence, parasitic capacitance CP1 is very high. Driver 10 must be quite large in order to charge and discharge capacitance CP1 at the high switching speed typically required. The net result is that driver 10 dissipates a large portion of the power utilized by the IC. For example, the clock driver in the Alpha RISC processor
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Callahan Timothy P.
Meetin Ronald J.
Zweizig Jeffrey
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