Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
1999-08-11
2008-09-23
Phan, Trong (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S201000
Reexamination Certificate
active
07428182
ABSTRACT:
An electronic circuit system has at least three macro circuits and a plurality of signal lines for connecting the macro circuits to one another into a loop. Each of the macro circuits includes a logic circuit and a memory circuit and has a plurality of input terminals and a plurality of output terminals. Signals are transmitted through the loop in a single specified direction in synchronization with a clock signal. Each of the macro circuits receives the signals at the input terminals thereof, accepts the signals if the signals are destined for the macro circuit, and transfers the signals to the output terminals thereof if the signals are not destined for the macro circuit. Even if the macro circuits simultaneously transmit signals, the electronic circuit system transmits the signals in the specified direction through the loop in synchronization with the clock signal up to destination macro circuits.
REFERENCES:
patent: 4860000 (1989-08-01), Kobayashi
patent: 5907554 (1999-05-01), Klos et al.
patent: 5930187 (1999-07-01), Sato et al.
patent: 6154406 (2000-11-01), Miyano et al.
patent: 6256604 (2001-07-01), Yabe et al.
IEEE Standard 802.5-1999, Token Ring Access Method and Physical Layer Specifications, Sep. 29, 1989, the entire publication.
IEEE Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture, published 1993, the entire publication.
Arent & Fox PLLC
Fujitsu Limited
Phan Trong
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