Electronic circuit structure with photoresist layer that has...

Details Electronic circuit structure with photoresist layer that has... Electronic circuit structure with photoresist layer that has...

1999-03-23

2002-02-12

Bowers, Charles (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S758000, C257S760000, C430S316000

Reexamination Certificate

active

06346748

ABSTRACT:

BACKGROUND
1. Field of the Invention
The present invention relates to methods of customization of integrated circuits, and more particularly, to an improved method of customizing integrated circuits without using expensive custom masks.
2. Related Art
Photolithography is used to transfer specific patterns onto semiconductor devices or integrated circuits during the fabrication process. A masking step transfers the pattern of a photomask onto a photoresist layer on the device surface by exposing the photoresist through the mask. Selected areas of the photoresist, based on the pattern of the mask, are then etched so that subsequent process steps, such as impurity introduction, oxidation, and metallization, can be performed. A semiconductor device with the desired electrical properties is then obtained after several of these application-specific masking and processing steps.
For example, a custom or application specific-integrated circuit (ASIC), frequently used to implement new circuit designs, may require several different custom masks during the fabrication process since each layer of the device needs to be specifically patterned. Because precision custom masks are costly to manufacture, a large quantity of each integrated circuit (IC) type must be produced in order for the fabrication process to be economical. However, as technology advances, circuit designs become more application-specific and are typically required at a much lower volume than the more generic ICs, thus making fabrication of such application-specific ICs more expensive per unit.
In an attempt to reduce the costs per unit of ASICs, a current practice is to use gate arrays to customize integrated circuits in order to minimize the number of different custom configuration mask steps. Gate arrays are mass-produced integrated circuits containing generic arrays of circuit elements (“gate array blanks”), which can be customized into application-specific ICs with a small number of masks defining custom interconnections of the circuit elements at the final steps of fabrication. The gate array blanks can be manufactured up to the customization steps and stored away until an order for a particular application-specific circuit is received. A precision configuration mask is then used to customize the specific gate arrays. However, the high costs of precision configuration masks limit the extent that costs and lead-time of ASICs manufacturing can be reduced.
An alternative method is to use direct write technology (techniques other than those where a photomask is the means of creating a pattern) on gate array processing to replace the steps requiring custom configuration masks. However, using programmable direct-write machines can still incur substantial costs to the manufacture of prototype and production ASICs. The feature sizes required to maintain a competitive die size require the use of expensive precision equipment with small spot sizes and low throughput. The low throughput results in a high processing cost for the customization step.
Accordingly, it is desirable to pattern photoresist so that fabricating customized integrated circuits can be accomplished without the drawbacks of conventional methods in order to reduce both lead-time and costs of designing and manufacturing ASICs.
SUMMARY
According to the present invention, a method is provided for patterning photoresist to create a customization method for an integrated circuit structure by combining precision and non-precision lithography without the need of a precision configuration mask, thereby reducing costs, complexity, and lead-time for fabricating an application specific integrated circuit (ASIC). Precision lithography, as mentioned above, is defined for these purposes as being capable of achieving the minimum design rule pitch, whereas non-precision lithography is defined for these purposes as being capable of no better than two times the minimum design rule pitch. One or more layers of metal (or non-metallic conductive material hereinafter referred to generally as “metal”) are patterned on the gate array blank, with the surface layer configured with multiple configuration points (hereinafter referred to generally as “cut points”), which represent possible cut points of a conductor. It is also possible to define cut points in lower conductor layers.
A layer of dielectric material is deposited on top of the metal layer(s) to be customized. The dielectric layer may or may not be planarized. A layer of photoresist is applied (either positive or negative polarity) over the dielectric layer. A standard precision mask or another precision technique (hereinafter referred to generally as “mask”) is used to define all possible cut points on the photoresist for any application or user. The photoresist is then developed, and the dielectric is etched down to the metal. Alternatively, via holes may also be patterned, developed, and etched with the same mask for later connection to an underlying metal layer. The word “via” in this document will be used to describe an opening in the dielectric which is used for the purpose of connecting to circuit elements on an underlying layer. Alternatively, instead of etching the dielectric down to the metal, the dielectric could be etched to a point just before the metal, resulting in a thin protective layer of dielectric over the metal. The device may be stored for later customization. When customization is desired, a second layer of photoresist is applied and then customized using a non-precision technique to select the desired features defined by the precision mask. Thus, the precision mask controls the feature size, while the non-precision step selects which features are desired.
In one embodiment of the present invention, the use of negative photoresist or other energy sensitive etch barrier (hereinafter referred to generally as “negative photoresist”) for the second application of photoresist is used on the device surface above the metal and dielectric layers. A programmable energy beam, (such as an electron or ion beam or targetable light ray), hereinafter referred to generally as a “laser”, is used to expose the resist in areas, typically larger than the openings, over the cut points to be protected and not acted upon. The resist is then developed to uncover the openings not selected by the laser. The device may then be processed through a metal etch or acted upon through these openings if the dielectric layer had previously been removed. If the thin dielectric layer still exists, then a dielectric etch is performed prior to etching the metal.
In another embodiment of the present invention, the use of positive photoresist for the second application of photoresist is used on the device surface above the metal and dielectric layers. A laser is used to expose the resist in areas, typically larger than the openings, over the cut locations to be opened and acted upon. The resist is then developed to uncover the openings selected by the laser. The device may then be processed through a metal etch or acted upon through these openings.
In another embodiment of the present invention, two layers are deposited between the potential metal cut points and the photoresist, which is applied and then customized using a laser. The application of the additional layer can be used as a potential final device protector and structural enabler, which may be required in some situations. Therefore, if the application of the additional layers occurs prior to customization, manufacturing cost and time can be reduced. The upper layer (e.g., a passivation layer) is deposited on top of a lower layer (e.g., a dielectric layer). The upper layer has etching properties dissimilar enough from the lower layer to limit the etch of the lower layer in order to maintain specific possible cut locations. After the laser has defined the specific locations of potential cut points, the resist is developed and the remaining layers are etched down to expose the metal. The device may then be processed through a metal etch or acted upon through these openings.
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