Electronic circuit package including plural semiconductor chips

Details Electronic circuit package including plural semiconductor chips Electronic circuit package including plural semiconductor chips

1995-09-05

1997-03-25

Lim, Krisna

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With structure for mounting semiconductor chip to lead frame

257635, 257638, 257678, 257700, H01L 2328

Patent

active

056147619

ABSTRACT:
An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayered substrate. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground. The bus line preferably includes two data bus lines, the semiconductor chips connected with one data bus line are formed on one side of the wiring substrate and the semiconductor chips connected with the other data bus line are formed on the other side of the wiring substrate.

REFERENCES:
patent: 4811288 (1989-03-01), Kleijne et al.
patent: 5016087 (1991-05-01), Haug et al.
patent: 5017993 (1991-05-01), Shibata
patent: 5072283 (1991-12-01), Bolger
patent: 5081563 (1992-01-01), Feng et al.
patent: 5185717 (1993-02-01), Mori
patent: 5237203 (1993-08-01), Massaron
patent: 5243208 (1993-09-01), Isomura et al.

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