Static information storage and retrieval – Format or disposition of elements
Reexamination Certificate
2001-02-28
2003-06-24
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Format or disposition of elements
C712S033000, C712S039000, C257S635000, C257S638000, C257S678000, C257S792000, C257S719000
Reexamination Certificate
active
06584004
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to miniaturization of an electronic circuit package and more particularly to an extra-small computer for use in space exploration.
A number of computers are being employed for various uses and the demand for smaller and lighter computers has also increased. Computers for use in space are required to be particularly smaller and lighter than conventional computers in order to decrease launching costs while increasing the payload.
As shown by a photograph 1 of “Development of LSI for Radiation Resistant 16-Bit Microprocessor”, pp. 10-411, Goke et al. Collection of Papers at 32nd Space Science and Technology Federation Lecture Meeting, a space computer is built of, for instance, discrete parts with reliable, resistant-to-environment single chips contained in one package.
There is no serious consideration given to decreasing the size and weight in the computer as comprised by the discrete parts.
On the other hand, a so-called multiple chip mounting technique, that is, the technique of mounting a plurality of bare chips on one wiring substrate for use on the ground is being studied. It has heretofore been arranged that, as shown in FIG. 3 of “Nikkei Micro Device”, pp. 32-40, December Issue, 1989, a wiring conductor to be connected to a bonding pad is led out of the bonding page.
It was not considered, however, to make wiring density uniform in this technique. The wiring density around the die bonding pad in particular is made extremely high and consequently effective wiring cannot be implemented. The wiring density in the outermost layer thus causes a bottleneck and the package size is not sufficiently reduced. As the via hole connecting the upper and lower layers occupied most of the area on the particular multilayer wiring substrate, the via holes account for a large percentage of area on the outermost layer, particularly around the die bonding pad.
With respect to a fault tolerant system, a checking unit for detecting errors and faults and a unit under check are accommodated in one and the same chip to reduce the size as described in “Trial Manufacture and Evaluation of Fault Tolerant Quartz Oscillation IC”, by Tsuchimura et al., Research Material, 24th FTC Study Meeting. With the diffusion of ASICs (Application Specified ICs) is particular, attempts have been made to add an MPU inspection circuit by making an ordinary MPU a core through the ASIC technology.
Faults and trouble affecting the whole chip were not taken into consideration in this technique described above. When the checking unit and the unit under check develop trouble simultaneously, the irregularity might not be detected.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a small and light electronic apparatus, in particular an electronic circuit package, with high reliability.
Another object of the present invention is to provide a small and light electronic apparatus in which the number of pins affixed to the outside of the package is reduced to prevent an increase of the package size.
Further still, yet another object of the present invention is to provide a small and light electronic apparatus in which the concentration of the wiring density is eased to prevent the increase of the package size.
According to the present invention, all semiconductor chips to be substantially connected by means of a bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayered substrate.
Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground. In a preferred embodiment of the present invention, there are wiring conductors from the wiring pads and via holes formed in the periphery and inside of the die bonding ground, and the wiring conductors are connected to other wiring conductors of a different wiring layer in the multilayer wiring substrate through the via hole.
Preferably, the bus line includes two data bus lines. The semiconductor chips connected with one data bus line are formed on one side of the wiring substrate and the semiconductor chips connected with the other data bus line are formed on the other side of the wiring substrate.
Preferably, the semiconductor chips include a checking unit and a unit under check.
Electronic apparatuses such as computers include a plurality of semiconductor chips that are normally connected to a bus having a number of signal lines. With discrete parts constituting the apparatus conventionally, an enormous number of pins are required as the signal lines connected to the bus are used to couple the internal and external devices of a package. In the present invention, as all of the semiconductor chips connected to the bus are formed into a single package, the number of signal lines connecting the inside and outside of the package is drastically reduced. In other words, the number of pins connecting the signal lines inside and outside of the wiring substrate decreases. As a result, the electric apparatus become small and light in comparison to conventional apparatuses.
Moreover, as each semiconductor chip is subjected to bare chips packaging, a fault of one chip does not influence other chips.
As lead-out lines can be formed from wiring bonding pads and via holes even under the die bonding ground, according to the present invention, the wiring density in the neighborhood of the wire bonding pads is prevented from centering there around. Therefore, the wiring density in each wiring layer is uniformized to the extent that they are effectively utilizable. As a result, the package becomes small.
The data line connected to MPU (Microprocessing Unit) ranges from 4, 8, 16, 32 up to 64 bits in width, for instance, depending on the kind of MPU. On the other hand, the data line connected to ROM (Read Only Memory) and RAM (Random Access Memory) ranges from 1, 4 up to 8 bits in width, for instance, depending on the kind of data line to be connected to the storage element. In other words, the data width of the storage element in this case is narrower than that of the MPU in many cases. Therefore, according to a preferred embodiment of the present invention, the data lines are grouped according to the width to be connected to the storage element and the storage element to be connected to the data line belonging to the same group is packaged on the same surface of the wiring substrate. As a result, the number of wiring layer-to-layer connections (via holes) is reduced and the wiring substrate is minimized in size as the area occupied by the via hole is decreased.
Although the semiconductor element often causes transistor (gate)-based trouble in many cases, the trouble may involve the whole element (chip). In the case of the trouble involving the whole chip, the electronic apparatus comprising the checking unit and the unit under check is unable to detect the trouble, thus making the addition of the checking unit meaningless.
Even when the checking unit and the unit under check are constructed of different packages, it will be essential for the checking signal lines to be provided between the checking signal lines. This will increase the size of the electronic apparatus.
Consequently, the checking unit and the unit under check are separately provided in respective chips on the same wiring substrate on a bare chip basis. The wiring substrate and the bare chips are connected by wire bonding into a single package. The omission of a fault involving the whole chip is thus prevented and furthermore, a small, light-weight electronic apparatus can be made available.
REFERENCES:
patent: 4144561 (1979-03-01), Tu
Akiyama Masatsugu
Ihara Hirokazu
Kanekawa Nobuyasu
Kawabata Kiyoshi
Okishima Tetsuya
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Nguyen Viet Q.
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