Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2007-01-31
2008-10-21
Ha, Nguyen (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
Reexamination Certificate
active
07439755
ABSTRACT:
An electronic circuit includes an output terminal and at least a first measuring FET. The second drain-source terminals of a plurality of FETS to be tested are interconnected with the first drain-source terminal of the first measuring FET and the output terminal. The second drain-source terminal of the first measuring FET is interconnected with a first biasing terminal. The first drain-source terminals of the FETS to be tested are interconnected with a second biasing terminal. A state machine is coupled to the gates of the FETS to be tested and the gate of the first measuring FET. The state machine is configured to energize the gate of the first measuring FET and to sequentially energize the gates of the FETS to be tested, so that an output voltage appears on the output terminal. Circuitry to compare the output voltage to a reference value is also provided.
REFERENCES:
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patent: 2005/0043908 (2005-02-01), Bhavnagarwala et al.
Mukhopadhyay, Saibal et al. 2007 IEEE International Solid-State Circuits Conference; ISSCC 2007/Session 22/Digital Circuit Innovations; “Statistical Characterization and On-Chip Measurement Methods for Local Random Variability of a Process Using Sense-Amplifier Based Test Structure”.
Terada, K. et al “A Test Circuit for Measuring MOSFET Threshold Voltage Mismatch.” Microelectronic Test Structures, 2003, International Conference, Mar. 2003, pp. 227-231.
Agarwal, K. et al. “A Test Structure for Characterizing Local Device Mismatches.” Proceeding of Symposium on VLSI Circuits, pp. 67-68, 2006.
Drego, N et al “A Test-Structure to Efficiently Study Threshold-Voltage Variation in Large MOSFET Arrays” Microsystems Technology Laboratories, MIT, Cambridge, MA, 2007.
Jenkins Keith A.
Kim Jae-Joon
Rao Rahul M.
Campbell Shaun
Ha Nguyen
International Business Machines - Corporation
Ryan & Mason & Lewis, LLP
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