Electronic circuit for determination of distances between refere

Details Electronic circuit for determination of distances between refere Electronic circuit for determination of distances between refere

1996-11-12

2000-01-11

Mai, Tan V.

Electrical computers: arithmetic processing and calculating

Electrical analog calculating computer

Particular function performed

G06G 700

Patent

active

060146850

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

1. Field of the Invention
This invention relates to an electronic circuit. More particularly, although not exclusively, it relates to an electronic circuit for determination of distances between reference and data points.
2. Discussion of Prior Art
Electronic circuits for determining Euclidean distances are known in the prior art. Such a circuit incorporates a stored quantity corresponding to a reference point and accepts as input a signal representing a data point. It produces a measure of the distance between the input signal and the stored quantity. Such circuits are useful in applications in which calculations of Euclidean distance would consume a substantial amount of computing capacity. In visual and speech recognition, together with other forms of pattern recognition, it is necessary to determine Euclidean distance between large numbers of input data points and each point in a large database of reference points.
U.S. Pat. No. 3,864,558 discloses a pair of field effect transistors (FETs) with programmable memories arranged to determine the square of the distance between two points represented by voltages. The FET memories are programmed by setting the threshold voltage. When the transistors are operated in saturation, the output current is dependent on the square of the difference between this programmed voltage and an applied gate voltage and hence is representative of the distance required. A p-channel and an n-channel FET are connected source to drain in antiparallel. The two gates are connected together such that only one FET conducts under an applied gate bias, the particular FET producing the distance representation being dependent on whether the applied gate voltage is greater or less than the stored threshold voltage. In this way an analogue for the square of the difference between a first magnitude and a second magnitude is produced regardless of the polarity of this difference. Using dissimilar-type FETs however makes it difficult to match device characteristics. Differing carrier mobilities and other physical characteristics mean that extreme difficulty is met in making allowance for the effects of device mismatch.
In "A Neural Network Capable of Forming Associations by Example", Neural Networks Vol. 2 pages 395-403, 1989, Hartstein and Koch disclose a similar arrangement of FETs. A two-transistor circuit is used in a neural network to represent the difference between a voltage input and a stored or learned value. Two metal oxide semiconductor field effect transistors (MOSFETs), a p-channel and an n-channel MOSFET are this time connected in parallel in a symmetric arrangement in order to obtain a symmetric output function for the neural network. Hartstein and Koch are not however concerned with Euclidean distance determination, but instead output function symmetry. This symmetry requires close matching of the characteristics of the p-channel and n-channel devices and if it is not achieved, the output of the circuit is not suitable for Euclidean distance determination.
In "Programmable Analogue VLSI for Radial Basis Function Networks", Electronics Letters 29(18), pages 1663-1665, September 1993, Churcher et al. describe a transconductance amplifier which produces an output current proportional to the square of the difference (distance) between an input voltage and a stored voltage maintained by a capacitor. The amplifier produces an approximation to the square of the Euclidean distance between the input and stored voltages. It is not suitable for applications such as pattern recognition requiring a large number of distance measuring circuits. It incorporates a number of transistors, two of which are considerably wider than the rest, which gives rise to difficulty as regards formation of large arrays. The transistors also suffer from high power consumption when operating in their saturation region.
A similar disadvantage is apparent in the circuit described in "CMOS Selfbiased Euclidean Distance Computing Circuit with High Dynamic Range", Electronics Letters 28 (

REFERENCES:
patent: 3864558 (1975-02-01), Yu
patent: 4999525 (1991-03-01), Park et al.
patent: 5336937 (1994-08-01), Sridhar et al.
Electronics Letters, vol. 28, No. 4, FEb. 13, 1992, pp. 352-354, XP 000292285, Landolt O et al, "CMOS Selfbiased Euclidean Distance Computing circuit with high dynamic range".

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