Amplifiers – Miscellaneous – Amplifier protection means
Reexamination Certificate
2003-06-11
2004-11-16
Nguyen, Khanh Van (Department: 2817)
Amplifiers
Miscellaneous
Amplifier protection means
C330S251000, C330S010000
Reexamination Certificate
active
06819177
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
Priority is claimed from European Application No. 02 013 141 filed Jun. 14, 2002 under 35 U.S.C. § 119.
FIELD OF THE INVENTION
The invention relates to an electronic circuit for a switching power amplifier, to a switching power amplifier, to an integrated circuit comprising an electronic circuit for a switching power amplifier and to a device comprising a switching power amplifier. The invention relates equally to a method for switching the output stage of a switching power amplifier.
BACKGROUND OF THE INVENTION
It is well known to employ switching power amplifiers in a variety of fields, e.g. in motor control, as switching RF (radio frequency) power amplifiers or as class D audio amplifiers, wherein amplifiers are categorized into class A, B, C, D, etc. by their properties. Typically, the load of a switching amplifier is a circuit containing an inductive component, for instance a motor or a speaker.
The main motivation to use switching power amplifiers is their high power efficiency. In portable devices, like mobile phones, a high power efficiency increases the operation time and decreases the heat dissipation and the resulting heating of the device. Another reason for using switching power amplifiers instead of linear amplifiers is the difficulties in implementing linear amplifiers with current low-voltage semiconductor technologies.
In switching power amplifiers, the output power provided to a load is controlled by switching power switches in the output stage of the amplifier. The output stage of a switching power amplifier can be implemented instance with PMOS and NMOS transistors or with PNP and NPN transistors in an inverter topology, where the transistors constitute controllable power switches of the output stage. The output stage can further be single-ended or differential.
FIG. 1
illustrates the principle of a single-ended output stage of a switching power amplifier. In
FIG. 1
, a PMOS transistor V
p
and an NMOS transistor V
n
, connected in series between a voltage supply
11
and ground
12
, constitute a single-ended output stage. The transistors V
p
, V
n
are controlled by a common input signal V
pwl
. The input signal V
pwl
has an alternating polarity and is provided by clocking means not shown in the figure. The output of the output stage is provided between the two transistors V
p
, V
n
. Currently, a load
13
is connected to this output. At the output of the output stage, a voltage V
out
is provided to the connected load
13
. Due to the alternating input signal V
pwl
, the output stage alternates between a first phase, in which a current is able to flow from load
13
via transistor V
n
to ground
12
, and a second phase, in which a current is able to flow from voltage supply
11
via transistor V
p
to load
13
. In a situation in which both transistors V
p
, V
n
are turned on, a current I
through
may flow from the branch comprising transistor V
p
to the branch comprising transistor V
n
. Alternatively, a separate input signal could be provided to the two transistors V
p
, V
n
.
A differential output stage, which is also referred to as H bridge, can be implemented by combining two appropriately clocked single-ended output stages. The load is arranged in this case between the outputs of the two single-ended switching stages.
FIG. 2
illustrates the principle of such a differential output stage.
On the one hand, a first PMOS transistor V
p1
, and a first NMOS transistor V
n1
are connected in series between a voltage supply
21
and ground
22
. On the other hand, a second PMOS transistor V
p2
and a second NMOS transistor V
n2
are connected in series between voltage supply
21
and ground
22
. The connection between transistors V
p1
, and V
n1
forms a first output of the differential output stage, and the connection between transistors V
p2
and V
n2
forms a second output of the differential output stage. Currently, a load
23
is connected between the first and the second output of the output stage. The output voltage at the first output is referred to as V
out1
, while the output voltage at the second output is referred to as V
out2
.
The four transistors are controlled such that the signals input on the one hand to transistors V
n1
, and V
p1
, and on the other hand to transistors V
2
and V
p2
have mainly an opposite, alternating polarity. This can be achieved in different ways. In one alternative, each of the transistors is controlled with a separate input signal. In another alternative, transistors V
p1
and V
n1
are controlled with a first input signal V
pwl1
, while transistors V
p2
and V
n2
are controlled with a second input signal V
pwl2
. The input signals V
pwl1
and V
pwl2
can be provided e.g. by a class BD modulation block. Class BD is used for three-level class D switching amplifiers. This second possibility is indicated in
FIG. 2
with a dashed line between a first input signal V
pwl1
fed to transistor V
n1
and transistor V
p1
, and with a dashed line between a second input signal V
pwl2
fed to transistor V
n2
and transistor V
p2
In a further alternative, all transistors are controlled by a single input signal. To this end, an input signal V
pwl1
is provided by clocking means (not shown) and fed to transistors V
n1
and V
p1
as in the second alternative, while the input signal for transistors V
n2
and V
p2
is obtained by an inverter
24
, to which input signal V
pwl1
is fed. Thereby, a separate second input signal V
pwl2
is not required. This possibility is indicated in
FIG. 2
with additional dotted lines.
Due to the alternating input signals, e.g. V
pwl1
and V
pwl2
, the output stage alternates between a first phase a, in which a current is able to flow from voltage supply
21
via transistor V
p2
, load
23
and transistor V
n1
to ground
22
, and a second phase b, in which a current is able to flow from voltage supply
21
via transistor V
p1
, load
23
and transistor V
n2
to ground
22
.
In both cases, i.e. in the case of a single-ended output stage and in the case of differential output stages, the transition between the respective first phase and the respective second phase can be realized by switching the power switches of the output stage in an overlapping mode or in a non-overlapping mode.
FIG. 3A
illustrates a non-overlapping switching and
FIG. 3B
an overlapping switching for the differential output stage presented in FIG.
2
. In both figures, the signals provided to the transistors V
n1
, V
p2
, V
n2
and V
p1
are shown for two consecutive transitions, more specifically for a first transition from phase a to phase b and for a subsequent transition back to phase a. For both transitions, a reference time is indicated by a vertical dotted line.
A non-overlapping mode can be achieved for a differential switching stage as depicted in
FIG. 2
by providing four separate switching signals for transistors V
p1
, V
n1
, V
p2
and V
n2
. In
FIG. 3A
, the non-overlapping signals supplied to transistors V
n1
and transistor V
p1
have a high level in the initial phase a, while the signals supplied to transistor V
p2
and transistor V
n2
have a low level in the initial phase a. Shortly before the reference time for the first transition from phase a to phase b, the signal supplied to transistor V
n1
is switched to a low level and the signal supplied to transistor V
p2
is switched to a high level. This has the effect of turning the transistors V
n1
and V
p2
off such that all power transistors are turned off. Shortly after the reference time for the first transition, the signal supplied to transistor V
n2
is switched to a high level and the signal supplied to transistor V
p1
is switched to a low level. This has the effect of turning the transistors V
n2
and V
p1
on. Shortly before the reference time for the second transition back from phase b to phase a, the signal supplied to transistor V
n2
is switched again to a low level and the signal supplied to transistor V
p1
is switched again to a high level. This has the effect of turning the transistors V
n2
Kauppinen Jani
Ruha Antti
Ruotsalainen Tarmo
Tervaluoto Jussi-Pekka
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