Electronic circuit arrangement for error-free analog/digital...

Coded data generation or conversion – Converter compensation

Reexamination Certificate

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C341S155000

Reexamination Certificate

active

07135998

ABSTRACT:
The present invention relates to a circuit arrangement for the error-free analog-to-digital conversion of N analog input signals Niin a plurality of digital output signals corresponding to the number N using exactly one analog-to-digital converter, wherein N>=1, wherein further N′ other redundancy inputs N′iare provided, and being fed to the said analog-to-digital converter, wherein the N and the N′ inputs are supplied to at least one analog multiplexer, and wherein the circuit arrangement has an error monitoring functionality, and each input signal Niis counter to the corresponding redundancy signal N′i. The invention also relates to the use of the circuit arrangement in electronic motor vehicle control units with an anti-lock function.

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“Properties of the Input Pattern Fault Model” Computer Design: VLSI in Computers and Processors, 1997, ICCD '97, Proceedings., 1997 IEEE International Conference on Austin, TX, USA Oct. 12-15, 1997, Los Alamitos, CA, USA, IEEE Comput. Soc, US Oct. 12, 1997, pp. 372-380, XP010251762 ISBN: 0-8186-8206-X, picture 4A.
PCT International Search Report of Application No. PCT/EP03/04805 dated Jul. 15, 2003.

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