Electronic circuit and method for half adder logic

Details Electronic circuit and method for half adder logic Electronic circuit and method for half adder logic

1991-09-05

1995-01-24

Envall, Jr., Roy N.

Boots, shoes, and leggings

36471501, 364787, G06F 750, G06F 700

Patent

active

053847245

ABSTRACT:
An electronic half adder circuit wherein an entire word of either 16 or 32 bits is divided into stages, carry is rippled within each stage and look-ahead carry is computed between the stages, having a dual gate look-ahead carry circuit for propagating a look-ahead carry bit between said stages. This is also a processor system. The system includes: memory for storing program instructions; a processor coupled to the memory for receiving predetermined ones of the program instructions; the processor comprises: an arithmetic unit; control circuitry for controlling the arithmetic unit in response to selected ones of the predetermined program instructions; a counter coupled to the control circuitry comprising half adder circuitry wherein a dual gate look-ahead carry circuit for propagates a look-ahead carry bit between the stages. Additionally, this is a half adder circuit for a device formed on a semiconductor substrate wherein the carry look-ahead circuit has two gates so that the layout space on the semiconductor is minimized and the speed of a signal through the dual gate carry look-ahead circuit is increased. Other devices, systems and methods are also disclosed.

REFERENCES:
patent: 4064421 (1977-12-01), Gajski et al.
patent: 4153939 (1979-05-01), Kudou
patent: 4286320 (1981-08-01), Granville
patent: 5027310 (1991-07-01), Dalrymple

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