Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Fusible link or intentional destruct circuit
Reexamination Certificate
2000-09-13
2002-02-12
Nuton, My-Trang (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Fusible link or intentional destruct circuit
C327S063000
Reexamination Certificate
active
06346847
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuits and, more particularly, to an electronic circuit and method for trimming an integrated circuit.
BACKGROUND OF THE INVENTION
When a high accuracy level is required of an integrated circuit, additional circuit portions must be associated with the circuit for the purpose of modifying certain circuit parameters at the integrated circuit testing stage. This modifying operation is commonly referred to as trimming.
The parameter modifications are usually performed at a wafer testing stage. Integrated circuits are fabricated in wafers formed of a semiconductor material, and an electrical wafer sort (EWS) test is conducted on the wafer prior to separating the circuits for subsequent packaging operations.
In special cases, trimming may also have to be carried out at the device final testing stage. One example of a circuit that requires this type of modification would be a step-down switching voltage regulator as commonly used in a variety of applications on account of its efficiency and accuracy.
New-generation regulators are to exhibit higher switching frequencies and allow for the use of smaller-size external components so as to keep their space requirements and cost low. In particular, the latter requirements involve a minimum presence of the necessary external components. Also required is a high accuracy throughout the operational range (e.g., supply voltage, temperature, etc.), and by reason of the required accuracy, certain basic parameters of a device must be further trimmed after the device packaging.
Prior approaches to modifying certain circuit parameters after the packaging step are known. These approaches essentially amount to using memory elements, wherein the information needed for trimming is saved. Such memory elements may be, for example, Zener diodes of the ZAP type. A feature of these components is that they operate as open circuits so long as the voltage thereacross does not exceed a predetermined threshold value. Upon this threshold value being exceeded and a large current is conducting, e.g., a few hundred milliamperes, the ZAP diode permanently changes its characteristic. In particular, the ZAP diode changes into a resistive component having a few ohms.
Another approach for modifying certain circuit parameters after the packaging step includes using integrated fuses which change their state, from short circuit to open circuit, upon an appropriate current being conducted therethrough. Yet another approach is integrated non-volatile memories, e.g., EEPROMs, EPROMs, etc., wherein an appropriate sequence of bits is stored for later use in forcing certain integrated microswitches to the closed or open state by suitable circuitry.
The above approaches do have merits, but also some deficiencies. The two approaches first mentioned above have the advantage of requiring no complicated managing circuitry. In fact, the fuses can be set by forcing a voltage and/or a current, but they need dedicated contact pins for addressing individual components at the EWS testing stage. In particular, additional pins must be specially provided for post-packaging trimming purposes.
There also have been approaches for minimizing the number of additional pins. For example, European Patent Application No. 98830521.5 discloses a method whereby the pins can be reduced in number as compared to other prior approaches, i.e., down to that of the trimming circuits plus one. This application is incorporated herein by reference in its entirety, and is assigned to the assignee of the present invention.
The methods based on the use of integrated memories actually require less pins. In fact, only two additional pins are needed. One each for a serial data input and for forcing the device to enter the trimming mode. In some cases, the additional two inputs can be obtained by utilizing a third logic level on a pin of the integrated circuit.
For example, by raising the voltage at a given pin above its specified upper limit, a comparator operates and places the circuit in the trimming mode. The internal data line can then be connected to the given pin once this is disconnected from the line to which it was connected in normal operation. In this way, all the circuitry needed for managing the trimming operations can be enabled.
This operation is usually carried out through the Reset and Enable pins. For example, RESET is taken away from the managing logic, and ENABLE is given to the affected analog portion. Such methods, although keeping the required number of pins low, have disadvantages as specified below.
They require more silicon area for the trim and memory write managing circuitry. This can be a problem where a large number of parameters are to be trimmed. With devices fabricated with mixed technologies, such as BCD technologies, the fabrication of integrated memories involves the addition of at least three extra masks to the basic process, which is cost-intensive.
With integrated circuits having a small number of pins, selecting the two pins to be used from the available ones and checking the state of the others may prove difficult. This is especially so when it is considered that the entire operation is to be carried out in real time.
Finally, there is a problem of simulating the effects of trimming. After the data is entered, but before it is permanently written into the memory, the effects of the trimming operation about to be carried out must be simulated. The simulation includes closing and/or opening internal switches and measuring the values of the parameters to be trimmed. The measurement often requires that the device condition be that of a normal operation so that a pin being used for entering the trim mode must be allowed to operate as normal. However, this results in the trim managing circuitry going out of control.
SUMMARY OF THE INVENTION
In view of the foregoing background, an advantage of the invention is to provide a trimming system with suitable structural and functional features for the trimming operations to be carried out in a straightforward manner, similar to a fuse arrangement but with no need for additional pins beyond those already provided in the integrated circuit to be trimmed.
This and other advantages and features are provided by an electronic circuit for carrying out a trimming operation on portions of an integrated circuit which are provided with at least first and second access terminals. The electronic circuit comprises memory elements, a regulation circuit for modifying, either temporarily or permanently, the state of the memory elements.
More particularly, the regulation circuit may include an error amplifier for comparing an output voltage of the portion of the integrated circuit to be trimmed with an internal voltage reference. A comparator may be provided which includes a first input connected to an output of the error amplifier and to the first access pin. A first switch may be connected between the output of the error amplifier and the first input of the comparator.
A second comparator may be provided which includes a first input connected to the second access pin, and an output connected to the first switch for control thereof. A second switch may be connected to the output of the error amplifier and to the first access pin. A serial interface may be connected to the second switch for receiving via the first access pin a data sequence relating to trimming the portion of the integrated circuit. A control logic circuit may be connected to the serial interface for controlling the trimming based upon the received data sequence.
The first and second switches are preferably in phase opposition. That is, the first switch is normally closed, and the second switch is normally open. An output of the second comparator may be connected to the serial interface, and the second switch may be controlled by an output of the second comparator. The control logic circuit further comprises a synchronous state machine connected downstream from the serial interface.
REFERENCES:
patent: 4843339 (1989-06-01), B
Capici Salvatore
Marino Filippo
Jorgenson Lisa K.
Nuton My-Trang
STMicroeletronics S.r.l.
LandOfFree
Electronic circuit and corresponding method for trimming an IC does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Electronic circuit and corresponding method for trimming an IC, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electronic circuit and corresponding method for trimming an IC will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2959277