Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
2000-02-15
2001-07-17
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S299000, C327S551000, C327S379000, C375S257000, C375S296000
Reexamination Certificate
active
06262614
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electronic circuit in which a clock line for transmitting a clock signal is extended, and more particularly an electronic circuit having a logic circuit operative by a clock signal in a macro and a block of a semiconductor integrated circuit of an LSI.
2. Description of the Related Art
Recently, as a semiconductor integrated circuit is integrated with a high density, a logic circuit is more complicated while a macro-processing technology is developed. This brings about many factors which affect to be disadvantageous in production of an integrated circuit for a stable operation. Particularly, as an increment of data sizes to be dealt with inside an LSI and a complication of commands are advanced, it begins that a long parallel wiring cannot be ignored by an influence of an increment of the number of bits in a macro and a block. According to the prior art, a high-integration is advanced by means of rationalization of logic circuits and efficient use of wiring. The high-integration is associated with a big problem also when a shield of noises emanating from a clock signal line is ensured. It is possible to suppress noises in such a way that a wiring of a shield wire is performed along the clock signal line. However, an insertion of the shield wire serves to degrade an integration degree of IC. With respect to a technology in which a degradation of the integration degree of IC is prevented, and a shield is performed, Japanese Patent Laid Open Gazette Hei.10-242282 discloses a technology that in a mode wherein a clock line to be shield is activated, a scan clock signal line on which a signal transmission is not performed is wired along the clock signal line to be shield, so that the scan clock signal line is used also as a shield wire.
As mentioned above, today, as high-integration complication of a circuit is further advanced, a bit length of data is elongated, such a long parallel wiring that a cross talk is generated in the block cannot be ignored on a design basis. Only such a concept that the scan clock signal line is wired along the clock signal line, as disclosed in the above-mentioned Japanese Patent Laid Open Gazette Hei.10-242282, is insufficient at the design stage for excluding the cross talk due to such a long wiring in block. Thus, it is considered that there is a need to improve the technology as mentioned above. There is considered, for example, a scan system and a reset system, a case where even if a certain length of wiring may be driven for a signal which is accepted in a slow cycle, a pulse width is increased while a miniaturization of an LSI circuit is advanced, so that a clock, which is short in a cycle and strong in a driving force, is used. In this case, while a propagation speed of the signal is ensured, it may happen that elongation of the wiring brings about such a situation that even if it is intended to hold the scan clock signal line at a predetermined position for a shield by the conventional scan system of drive, it is insufficient to shield a clock noise emanated from the clock signal line, which is strong in a shield phenomenon.
SUMMARY OF THE INVENTION
In view of the foregoing, it is an object of the present invention to provide an electronic circuit having a structure capable of performing sufficiently clock shielding without degradation of an integration degree of IC.
To achieve the above-mentioned objects, the present invention provides an electronic circuit comprising:
a clock driver for generating a clock signal;
a clock line on which the clock signal generated by said clock driver is transmitted;
a shield-cum-signal line extending along said clock line serving optionally for transmission of a predetermined signal and for shielding of a noise generated from said clock line in accordance with a mode;
a transfer gate for transferring a transmitted signal to said shield-cum-signal line, said transfer gate turning on or off in accordance with a mode; and
a transistor disposed between said shield-cum-signal line and a power source, said transistor turning on when said transfer gate turns off and turning off when said transfer gate turns on in accordance with a mode.
Any one is acceptable, as the above-referenced “power source”, which is constant in potential. Consequently, it is acceptable that the “power source” is the ground, or ones which are kept on a constant potential to the ground.
Further, the above-referenced “transistor” typically implies an N-channel transistor in a MOS structure. But it is acceptable that the “transistor” is a P-channel transistor.
The electronic circuit according to the present invention is provided with the transistor as mentioned above. Thus the use of the transistor, which has a size associated with a noise level of noises emanated from the clock line, makes it possible to effectively shield the noises emanated from the clock line. On the other hand, with respect to the transfer gate, a small size of transfer gate can be used. Further, as compared with the conventional driving system in which the shield-cum-signal line is driven by an inverter for instance, according to the conventional driving system, in case of the inverter drive, two transistors of an N-channel transistor and a P-channel transistor, as a large size of transistor, are needed. To the contrary, according to the present invention, it is permitted to use only one transistor. Thus, it is possible to expect an improvement of an integration degree of IC also in combination use with the transfer gate.
In the electronic circuit according to the present invention as mentioned above, it is acceptable that the electronic circuit further comprises a plurality of flip-flops,
wherein said electronic circuit has a usual operating mode and a scan test mode for performing a scan test,
said clock driver generates, in the usual operating mode, the clock signal to operate the flip-flops, and
said shield-cum-signal line serves, in the scan test mode, to transmit a scan clock signal for operating the flip-flops.
The scan test is a test method which is widely used. It is general that a circuit for the scan test is incorporated into the conventional LSI too. According to the electronic circuit of the present invention, it is possible to use a signal line, which serves to transmit a scan clock signal for the scan test, as the shield-cum-signal line.
Further, in the electronic circuit according to the present invention as mentioned above, it is preferable that said transistor is disposed at a plurality of portions of said shield-cum-signal line.
In the event that the clock line and the shield-cum-signal line are elongated, the disposition of a large transistor at the driving end of the shield-cum-signal line may bring about a delay of a predetermined signal to be transmitted through the shield-cum-signal line. At that time, according to the present invention, it is possible to expect a sufficient shielding effect throughout the long wiring path, without the use of an extremely large transistor at the driving end.
Furthermore, in the electronic circuit according to the present invention as mentioned above, it is preferable that the electronic circuit further comprises a plurality of flip-flop cells each incorporating therein constructive elements of a flip-flop,
wherein said transistor is incorporated into at least one of said plurality of flip-flop cells.
The flip-flop cell, into which the above-mentioned transistor is incorporated, is prepared beforehand in the form of a library, and is suitably arranged. This feature makes it possible to ensure a shielding effect and also makes a design easy.
Still further, in the electronic circuit according to the present invention as mentioned above, it is preferable that the electronic circuit further comprises an area in which a plurality of flip-flops are arranged vertically and horizontally,
wherein said clock line and said shield-cum-signal line are extended in either one direction of length and breadth, and a control line, which serves to
Armstrong Westerman Hattori McLeland & Naughton LLP
Cunningham Terry D.
Fujitsu Limited
Tra Quan
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