Electronic chip package

Details Electronic chip package Electronic chip package

2001-09-10

2003-04-08

Lam, Cathy (Department: 1775)

Stock material or miscellaneous articles

Web or sheet containing structurally defined element or...

Composite having a component wherein a constituent is liquid...

C428S308400, C428S317100, C428S325000, C428S344000, C428S421000, C174S255000, C174S258000, C174S259000, C257S702000, C257S703000, C257S705000, C257S729000

Reexamination Certificate

active

06544638

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of integrated circuit packaging, methods of manufacturing integrated circuit packaging interconnections, and more particularly, to methods and apparatuses for forming vias in a multilayered substrate having alternating dielectric and conductive layers.
BACKGROUND OF THE INVENTION
Interconnection and packaging related issues are among the main factors that determine not only the number of circuits that can be integrated on a chip, but also the performance of the chip. These issues have gained in importance as advances in chip design have led to reduced feature sizes of transistors and enlarged chip dimensions. Industry has come to realize that merely having a fast chip will not result in a fast system; it must also be supported by an equally fast and reliable package or packaging.
Essentially, a package or packaging supplies the chip with signals and power, and performs other functions such as heat removal, physical support and protection from the environment. Another important function is simply to redistribute the tightly packed I/Os off the chip to the I/Os of a printed wiring board.
An example of a package-chip system is a “flip-chip” integrated circuit mounted on an area array organic package. Flip-chip mounting entails placing solder bumps on a die or chip, flipping the chip over, aligning the chip with the contact pads on a substrate, and re-flowing the solder balls in a furnace to establish bonding between the chip and the substrate. This method is advantageous in certain applications because the contact pads are distributed over the entire chip surface rather than being confined to the periphery as in wire bonding and most tape-automated bonding (TAB) techniques. As a result, the maximum number of I/O and power/ground terminals available can be increased, and signal and power/ground interconnections can be more efficiently routed on the chips.
With flip-chip packaging, thermal expansions due to mismatches between the semiconductor chip and the substrate can cause strains at the bumps, and thus, could lead to failure. Regardless of which packaging technique is employed, material issues such as the aforementioned thermally induced strain causes a chip package designer to select and match materials with great care.
In the manufacture of integrated circuit packaging, the chip package designer attempts to obtain ever greater wiring densities while at the same time forming interconnections between adjacent layers that provide reliable circuits with as little inductance and resistance as possible. Thus, the formation of high quality via holes, or vias, that are used for interconnections, is an important aspect of forming high quality interconnections.
It has been known to use lasers to form vias in multilayered ceramic packages or substrates. For example, U.S. Pat. No. 5,378,313 to Pace discloses a process for manufacturing a multilayer hybrid for a ceramic multichip module (MCM-C) device that uses a metallic conductive pattern layer formed on an inorganic insulating layer. Vias having a diameter of between 25-125 &mgr;m are formed by laser drilling through an inorganic insulating layer for making electrical connections between conductive pattern layers. According to Pace, the overall thickness of the inorganic insulating layers should be less than 50 &mgr;m, preferably less than 40 &mgr;m, and more preferably less than 30 &mgr;m.
It has been known to form blind-vias using lasers operating predominately in a scanning mode using excimer gas lasers in the 193 nanometer (nm), 248 nm, and 308 nm ranges. The beam is scanned over a metal mask and then focused to a spot through apertures formed in the mask. However, the mask tends to absorb the laser energy, thus generating heat distortion, forming oxides and/or redepositing ablated material onto the surface of the mask.
The current trend in integrated circuit packaging technology is shifting from the ceramic substrate-based interconnection circuit devices to organic substrate-based interconnection circuit devices for single chip modules (SCMs) and multi-chip modules (MCMs) because the organic substrate-based devices are less expensive to process and fabricate. However, the lasers known for via formation in the past are not generally suitable for use with organic-based multilayer packages.
The MCM-C devices are typically formed by multilayer conductive patterns that are combined together in a co-fired monolithic structure. Each layer of an MCM-C device is formed from a green ceramic tape having a conductive pattern printed on the green tape. Vias for interconnecting the different layers are punched, or laser drilled, through a green tape layer. The individual green tape layers are then laminated together and co-fired to form the monolithic structure. MCM-C devices suffer from lamination size variations caused by shrinkage when fired.
When relatively thinner conventional organic substrate-based interconnection circuit devices are attached to an integrated circuit die, the thinner structures of the devices flex and bend more readily than the thicker ceramic substrate devices because of differences in the coefficients of thermal expansion (CTE) between the materials used in the organic substrate devices and the integrated circuit die or chip, and because of mechanical stresses that occur when the interconnection devices and the chips are attached. Relatively thicker conventional organic-substrate-based interconnection devices do not experience the same degree of flexure as the relatively thinner conventional devices primarily because of the differences in relative stiffnesses. That is, the flexural or bending modulus of an interconnection device increases proportionally to the thickness of the device cubed. So, an interconnection device that is twice as thick as another interconnection device made of the same substrate has a flexural modulus that is eight times greater.
A need exists for an integrated circuit package, and methods of making such a package, made of organic-based-substrate materials that have small via diameters and high via aspect ratios, and that provide high conductor routing density. Additionally, there is a need for an interconnection device formed from an organic dielectric substrate material that has a coefficient of thermal expansion (CTE) that matches the CTE of a printed circuit board and the CTE of an integrated circuit chip to which the interconnection device is bonded so that the bending effects caused by CTE mismatch are minimized.
SUMMARY OF THE INVENTION
An electronic chip package is provided having a laminated substrate. The laminated substrate includes at least one conductive layer and at least one dielectric layer which is bonded to the conductive layer. The dielectric layer has a glass transition temperature T
g
greater than 200° C. and a volumetric coefficient of thermal expansion of ≦75 ppm/° C. A semiconductor device is electrically attached to the laminated substrate.
The present invention provides an electronic chip package having vias and a method for making vias in an interconnection circuit device. The vias formed by the present invention have smaller entrance diameters, exit diameters, greater aspect ratios and lower average via resistances than vias formed by conventional techniques. Additionally, the present invention provides an improved high-volume manufacturing yield over conventional approaches because a high degree of manufacturing repeatability is ensured by the present invention. For example, vias produced according to the present invention have low entrance and exit diameter variances, low average via resistances, and correspondingly low via resistance variances.


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