Electronic camera

Details Electronic camera Electronic camera

1998-10-08

2003-05-20

Garber, Wendy R. (Department: 2612)

Television

Camera, system and detail

Combined image signal generator and general image signal...

C348S230100, C348S223100

Reexamination Certificate

active

06567123

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to electronic cameras having high pixel density image pick-up devices and, more particularly, to electronic cameras which can provide smooth moving images to a liquid crystal display for recorded image confirmation with contracted evaluation value computing circuit for AE (automatic exposure), AF (auto focus) and AWB (auto white balance).
Electronic cameras generally called digital cameras or cam coders have an AE, an AF and an AWB function. For intelligently carrying out the processes of executing these functions, a method of control, in which evaluation values are obtained by dividing the image area into a plurality of divisions, is well known in the art. An exemplified construction of the electronic camera, in which the AE, AF and AWB are controlled by dividing the image area into a plurality of division areas, will now be described with reference to the block diagram shown in FIG.
1
. An image is focused through a lens system
1
including a focus adjusting lens and an iris
2
for light dose adjustment on a CCD image pick-up device
3
. The CCD image pick-up device
3
photoelectrically converts the focused image into an electric signal. A photographing circuit
4
processes the electric signal to generate an image signal. An A/D converter
5
converts the image signal to a digital signal.
When a CPU
17
detects that a recording mode has been set up by a mode setting switch
18
, it controls the entire camera for operation in the recording mode. The digital signal from the A/D converter
5
is tentatively accumulated in a buffer
6
, and then converted in a D/A converter to an analog signal, which is provided to a liquid crystal display (LCD)
9
. The user can utilize the liquid crystal display as a view finder for setting the image to be picked up by watching the image displayed on the liquid crystal display
9
. A compressor/decompressor
8
compresses the digital signal accumulated in the buffer
6
for recording the compressed digital signal as image data in a recording memory
10
. When the CPU
17
detects that a play mode has been set up by the mode setting switch
18
, it controls the entire camera for operation in the play mode. In this camera, the compressor/decompressor
8
decompresses the image data stored in the recording memory
10
, and the expanded image data is tentatively accumulated in the buffer
6
. The D/A converter
7
then converts the accumulated digital data to analog data, which is provided to the liquid crystal display
9
. The user thus can confirm the recorded image by watching the image displayed on the liquid crystal display
9
. The digital image signal from the A/D converter
5
is also provided to an AE, an AF and an AWB data detector
11
,
12
and
13
, respectively. The AE data detector
11
extracts a low frequency component of the image signal. A 1-st area integrator
14
a
integrates the extracted low frequency component for each of a plurality of divisions of the image area by using either an evaluation value memory
15
a
or
15
b
. Each integration value is preserved directly as AE evaluation value in the evaluation value memory
15
a
and
15
b.
Now, area integration executed by accessing the two evaluation value memories
15
a
and
15
b
will now be described with reference to the timing chart shown in FIG.
2
. Data A which is obtained by exposure in a 1-st VD (vertical sync signal) period, is integrated in a 2-nd VD cycle in the 1-st area integrator
14
a
. When the 1-st area integrator
14
a
makes the memory accessing, it always makes memory accessing, and exclusively uses one evaluation value memory. Meanwhile, the CPU
17
seeks to read the result of area integration result of data A (i.e., evaluation result A′) from the evaluation value memory in a certain part of a 3-rd VD cycle. In this period, however, the 1-st area integrator
14
a
also seeks to make area integration of data B obtained by exposure in the 2-nd VD cycle by using the evaluation value memory. This means that it is inconvenient if only a single evaluation value memory is provided. Where two evaluation value memories are provided, one of them can be used for the area integration, while using the other for reading out the result of area integration (i.e., evaluation value). By alternately using these two evaluation value memories, it is possible to obtain the evaluation value for each VD (frame) period. For this reason, two evaluation value memories are provided for each of the 1-st to 3-rd area integrators
14
a
to
14
c.
Referring to the timing chart of
FIG. 2
, in the 2-nd VD cycle the 1-st area integrator
14
a
executes area integration of data A by using the evaluation value memory
15
a
, in the 3-rd VD cycle the CPU
17
reads out the result of area integration of data A, i.e., evaluation value A′, from the evaluation value memory
15
a
while the 1-st area integrator
14
a
makes area integration of data B by using the evaluation value memory
15
b
, and in the 4-th VD cycle the CPU
17
reads out evaluation value B′ of data B from the evaluation value memory
15
b
while the 1-st area integrator
14
a
executes area integration of data C by using the evaluation data memory
15
a.
Referring back to the block diagram of
FIG. 1
, the AFD data detector
12
extracts a high frequency component of the image signal. A 2-nd area integrator
14
b
integrates the extracted high frequency component for each of the plurality of image area divisions by using either an evaluation value memory
15
c
or
15
d
. The result of the area integration is directly stored as AF evaluation value in either of the evaluation value memories
15
c
or
15
d
. The AWB data detector
13
separates color components (for instance R, G and B components) from the image signal. A 3-rd area integrator
14
c
integrates each separated color signal for each of the plurality of image area divisions by using either an evaluation value memory
15
e
or
15
f
. The result of the area integration is directly stored as AWB evaluation value in either of the evaluation value memories
15
e
and
15
e
. The CPU
17
can obtain the AE, AF and AWB values through the multiplexer
16
. Since it is possible time-wise to read the three, i.e., AE, AF and AWB, evaluation values in one VD cycle, the CPU
17
can take out a desired evaluation value at a desired timing. Of curse, the CPU
17
can take the three evaluation values for each VD frame.
The CPU
17
controls the gain of the image signal from the image pick-up circuit
4
according to the AF evaluation value. Also, the CPU
17
controls the shutter speed of a device shutter in a CCD driver
19
. (By the term “device shutter” is meant what can provide an equivalent effect to opening and closing a mechanical shutter by varying the photoelectric charge storage time of the image pick-up device.) The CPU
17
further drives the iris
2
, which is coupled to a motor
22
, via a motor driver
20
for exposure setting. The CPU
17
further drives a focusing lens, which is coupled to a motor
23
, via a motor driver
2
according to the AF evaluation value. The CPU
17
further controls the gain of the image signal from the image pick-up device
4
for each color according to the AWB evaluation value, for white balance setting.
As shown above, the electronic camera having the construction as shown in
FIG. 1
, can execute intelligent AE, AF and AWF processes. On the demerit side, however, the camera requires three area integrators and six memories therefor, thus leading to an extremely large circuit scale.
FIG. 3
shows a different example of the electronic camera construction, which uses a common area integrator and common evaluation value memories for decreasing circuit scale. A different part of the electronic camera shown in
FIG. 3
from the one shown in
FIG. 1
will be described. The outputs of the AE, AF and AWF data detectors
11
,
12
and
13
are selectively coupled by a switch
24
to a single area integrator
14
. Actually, since the AE, AF and AWF ev

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