Electronic ballast employing a startup transient voltage...

Electric lamp and discharge devices: systems – Current and/or voltage regulation – Automatic regulation

Reexamination Certificate

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Details

C315S224000, C315S324000, C315SDIG005

Reexamination Certificate

active

06376999

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a fluorescent lamp ballast and, more particularly, to circuitry for providing transient prevention for use with a dimmable cold cathode fluorescent lamp (CCFL) ballast.
2. Description of the Related Art
Open circuit protection is often required in electronic ballasts for safety and reliability reasons. When the lamps, i.e., loads, are not connected to the ballast outputs, there will be a very large undesirable voltage occurring across the ballast outputs if protection is not in place. This unloaded case can result in an output voltage which may be on the order of 5× higher than a nominal output with the lamps connected (e.g., 3500 volts instead of 700 volts). The overvoltage condition can damage ballast components and/or cause the ballast running into an unexpected state, and thus eventually damaging the ballast.
Overvoltage protection is required in lamp driving circuits as described in U.S. Pat. Nos. 5,680,017, 6,011,360 and 6,084,361; the contents of each of which are hereby incorporated herein by reference.
FIG. 1
illustrates a block diagram of the liquid crystal display (LCD) backlight inverter in accordance with the prior art, designated generally by reference numeral
100
. The LCD backlight inverter
100
typically comprises a power stage module
6
for operating a lamp(s), such as L
1
8
and L
2
10
. Lamps
8
and
10
may be, but are not limited to illuminating a liquid crystal display (LCD) of a desktop computer (not shown). The LCD backlight Inverter
100
further comprises a startup logic module
16
, a short/open protection module
15
, and a control IC (integrated circuit)
20
. It is noted that a pulse width modulating module may be incorporated in the configuration of
FIG. 1
with minor modifications to control signals between the IC
20
and the power stage module
6
.
IC
20
performs a number of functions including: regulating lamp power by sensing lamp current and voltage, receiving and outputting control and non-control signals, generating an internal oscillation for driving power switches (not shown) included as part of the power stage module.
FIG. 1
shows two control signals G
1
and G
2
which represent output control signals for driving half bridge switches internal to the power stage module
6
, which regulates the output power of transformers internal to power stage module
6
to drive L
1
and L
2
. The startup logic module
16
powers the IC
20
(See signal Chip_V
dd
) under normal operating conditions and prevents IC
20
from receiving power under fault conditions or whenever an “enable” signal to the startup logic module
16
is not activated. At startup, signal Chip_V
dd
will ramp up to reach a threshold voltage, V
don
. The IC
20
is said to be in an oscillation mode after the threshold voltage V
don
is reached. The startup logic module
16
is further used to disable IC
20
to prevent detected overvoltages from damaging IC
20
, as described further below.
FIG. 2
is an illustration depicting particular elements of FIG.
1
and additionally provides a detailed circuit diagram of the power stage module
6
of FIG.
1
. The power stage module
6
is based on a voltage-fed, half-bridge resonant converter for providing a high starting voltage (e.g., >1700 Vrms) to ignite the lamps and a current source drive to run the lamps in the on-state with high efficiency (i.e., >85%). As shown in
FIG. 2
, power stage module
6
comprises two power switches, M
1
31
and M
2
32
. In the present embodiment, M
1
31
is a high side power MOSFET switch and M
2
32
is a low side power MOSFET switch. The power switches may also be embodied as insulated gate bipolar transistors (IGBTs) in alternate embodiments. The half bridge switches M
1
and M
2
are each driven in a steady state mode of operation, with non-overlapping gate signals, G
1
and G
2
, respectively. As shown, the power switches are arranged in a half bridge topology, having a common point
33
for sourcing an L-L-C resonant circuit comprising inductor T
3
37
, transformers T
1
36
, T
2
38
, and capacitor C
39
and C
40
. Lamp L
1
8
is shown connected to a secondary winding of transformer T
1
36
and lamp L
2
10
is connected to a secondary winding of transformer T
2
38
without ballasting capacitors. In the exemplary embodiment, lamps L
1
8
and L
2
10
are cold cathode fluorescent lamps (CCFL). It is well known to those in the art that other types of loads may be substituted for the lamps L
1
8
and L
2
10
in different applications. By not using ballasting capacitors, the reactive power handled by the output transformers is minimized. The two lamps L
1
8
, L
2
10
share a common ground and a common lamp current sensing resistor RSENSE.
Power switch M
2
32
is driven to conduct alternately by a control signal G
2
46
provided by IC
20
, and power switch M
1
31
is driven to conduct alternately by a control signal G
1
48
provided by IC
20
. Lamp power regulation is provided by closed-loop feedback control. A Lamp voltage is obtained from a tightly coupled winding on the secondary of output transformers T
1
36
and T
2
38
, while the lamp current is detected across resistor RSENSE tied in series with the lamp. The lamp current detected across RSENSE is provided as an input to pins LI
1
and LI
2
of IC
20
to represent the average current in the lamp. The IC
20
then drives the half bridge frequency in a direction to achieve the desired lamp power as dictated by a reference input to the controller. In this case, the reference input is the DIM input pin to the controller.
With continued reference to
FIG. 2
, the startup sequence of the liquid crystal display backlight inverter of the prior art will be described to illustrate the limitations of the prior art regarding the inability to protect against the occurrence of a startup overvoltage transient.
Initially, (i.e., during startup) power switches M
1
31
and M
2
32
are in a nonconducting state. Input signal Chip_V
dd
43
is off as a consequence of ENABLE
42
being off. Inverter
100
input V
dd
44
is applied to the circuit and consequently a node voltage VNODE
40
at a common point between C
3
40
and C
1
41
will be charged to V
dd
/
2
as a consequence of C
3
40
and C
1
41
having the same capacitance value. At the point in time when the ENABLE signal
42
is switched on, IC
20
supply Chip_V
dd
43
, which is sourced from supply voltage V
dd
44
, slowly charges from zero volts and is applied to the pin of IC
20
labeled V
dd
. IC
20
supply Chip_V
dd
43
slowly charges to reach a threshold voltage V
don
. Prior to reaching the threshold level, V
don
, in response, IC
20
will activate pin G
2
to cause output signal G
2
to maintain M
2
32
in an ON state, and high side power switch M
1
31
in an OFF state.
As previously stated, IC
20
does not oscillate prior to Chip_V
dd
reaching a threshold level V
don
. Prior to IC supply Chip_V
dd
43
reaching the threshold level V
don
, M
2
32
is maintained in an ON state thereby creating a path through T
2
, T
1
, T
3
and M
2
, thereby allowing node VNODE
40
to discharge to zero. This creates a DC offset (asymmetry) in sensing inductor T
3
37
which is converted to an unbalanced sensing signal along line
54
. The voltage asymmetry is sensed by input inductor current sensing pin RIND of IC
20
which drives the half bridge frequency undesirably lower towards the resonant frequency. In particular, signals G
2
and G
1
begin to prematurely oscillate at an undesirable low frequency thus driving the low and high side power switches M
2
32
and M
1
31
, respectively, at the undesirable low frequency rate. The low switching rate is undesirable in that it is near the resonant frequency of the L-L-C resonant circuit formed by resonant inductor T
3
, transformers T
1
36
, T
2
38
, and capacitors C
39
and C
40
, thereby causing the startup voltage transient.
The undesirable low frequency rate at which power switches M
1
31
and M
2
32
are driven is a consequence of the co

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