Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2000-12-29
2002-05-14
Paladini, Albert W. (Department: 2841)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S261000, C257S692000, C257S698000, C257S773000, C361S760000
Reexamination Certificate
active
06388207
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to electronics packaging. More particularly, the present invention relates to an electronic assembly that includes a substrate comprising conductive trenches for providing improved power delivery and signal integrity, and for reducing inductance, in an integrated circuit package for a high performance integrated circuit, and to manufacturing methods related thereto.
BACKGROUND OF THE INVENTION
Integrated circuits (IC's) are typically assembled into packages by physically and electrically coupling them to a substrate made of organic or ceramic material. One or more IC's or IC packages can be physically and electrically coupled to a substrate such as a printed circuit board (PCB) or card to form an “electronic assembly”. The “electronic assembly” can be part of an “electronic system”. An “electronic system” is broadly defined herein as any product comprising an “electronic assembly”. Examples of electronic systems include computers (e.g., desktop, laptop, hand-held, server, etc.), wireless communications devices (e.g., cellular phones, cordless phones, pagers, etc.), computer-related peripherals (e.g., printers, scanners, monitors, etc.), entertainment devices (e.g., televisions, radios, stereos, tape and compact disc players, video cassette recorders, MP3 (Motion Picture Experts Group, Audio Layer 3) players, etc.), and the like.
In the field of electronic systems there is an incessant competitive pressure among manufacturers to drive the performance of their equipment up while driving down production costs. This is particularly true regarding the packaging of IC's on substrates, where each new generation of packaging must provide increased performance, particularly in terms of an increased number of components and higher clock frequencies, while generally being smaller or more compact in size.
An IC substrate may comprise a number of insulated metal layers selectively patterned to provide metal interconnect lines (referred to herein as “traces”), and one or more electronic components mounted on one or more surfaces of the substrate. The electronic component or components are functionally connected to other elements of an electronic system through a hierarchy of electrically conductive paths that include the substrate traces. The substrate traces typically carry signals that are transmitted between the electronic components, such as IC's, of the system. Some IC's have a relatively large number of input/output (I/O) terminals (also called “lands”), as well as a large number of power and ground terminals or lands. The large number of I/O, power, and ground terminals requires that the substrate contain a relatively large number of traces. Some substrates require multiple layers of traces to accommodate all of the system interconnections.
Traces located within different layers are typically connected electrically by vias (also called “plated through-holes”) formed in the board. A via can be made by making a hole through some or all layers of a substrate and then plating the interior hole surface or filling the hole with an electrically conductive material, such as copper or tungsten.
One of the conventional methods for mounting an IC on a substrate is called “controlled collapse chip connect” (C
4
). In fabricating a C
4
package, the electrically conductive terminations or lands (generally referred to as “electrical contacts”) of an IC component are soldered directly to corresponding lands on the surface of the substrate using reflowable solder bumps or balls. The C
4
process is widely used because of its robustness and simplicity.
As the internal circuitry of high performance ICs, such as processors, operates at higher and higher clock frequencies, and as ICs become more dense and operate at higher and higher power levels, a number of manufacturing and operational factors can reach unacceptable levels. These factors include manufacturing cost and complexity, package size, inductance and capacitance levels, heat dissipation, signal integrity, and product reliability.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a significant need in the art for methods and structures for packaging a high performance IC on a substrate that provide increased power delivery and signal integrity, and decreased inductance levels.
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Figueroa David G.
Li Yuan-Liang
Sankman Robert L.
Walk Michael
Intel Corporation
Paladini Albert W.
Schwegman Lundberg Woessner & Kluth P.A.
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