Electronic assembly with stacked integrated circuit die

Details Electronic assembly with stacked integrated circuit die Electronic assembly with stacked integrated circuit die

2006-04-18

2006-04-18

Ngo, Hung V. (Department: 2831)

Electricity: conductors and insulators

Boxes and housings

Hermetic sealed envelope type

C257S777000, C257S778000, C257S713000

Reexamination Certificate

active

07030317

ABSTRACT:
An electronic assembly with a plurality of stacked integrated circuit (IC) die includes a base substrate, a first IC die, a second IC die, a signal routing first interconnect and a signal routing second interconnect. The first interconnect is partially positioned between the first and second IC dies. The second interconnect is partially positioned adjacent the first side of the second IC die. The first interconnect couples a first contact of the first IC die to a first trace of the base substrate and a second contact of the second IC die to a second trace of the base substrate. The first and second interconnects, in combination, couple the first contact of the second IC die to the first trace.

REFERENCES:
patent: 6150724 (2000-11-01), Wenzel et al.
patent: 6291881 (2001-09-01), Yang
patent: 6507098 (2003-01-01), Lo et al.
patent: 6559525 (2003-05-01), Huang
patent: 6590281 (2003-07-01), Wu et al.
patent: 6650006 (2003-11-01), Huang et al.
patent: 6707140 (2004-03-01), Nguyen et al.

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