Electricity: electrical systems and devices – Electrostatic capacitors – Fixed capacitor
Reexamination Certificate
2001-06-14
2003-10-21
Berhane, Adolf D. (Department: 2836)
Electricity: electrical systems and devices
Electrostatic capacitors
Fixed capacitor
C361S763000
Reexamination Certificate
active
06636416
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to apparatus for providing capacitance to an electronic circuit, and more particularly to providing capacitance to an integrated circuit load, and methods of manufacturing an electronic assembly that includes discrete capacitors electrically attached to a housing.
BACKGROUND OF THE INVENTION
Electronic circuits, and particularly computer and instrumentation circuits, have in recent years become increasingly powerful and fast. As circuit frequencies continue to escalate, with their associated high frequency transients, noise in the power and ground lines increasingly becomes a problem. This noise can arise due to inductive and capacitive parasitics, for example, as is well known. To reduce such noise, capacitors known as bypassing capacitors are often used to provide a stable signal or stable supply of power to the circuitry. Capacitors can also be used to suppress unwanted radiation, to dampen voltage overshoot when an electronic device (e.g., a processor) is powered down, and to dampen voltage droop when the device powers up.
Bypassing capacitors are generally placed as close as practical to a die load or “hot spot” in order to increase the capacitors' effectiveness. Often, the bypassing capacitors are surface mounted to the die side or land side of the package upon which the die is mounted, or embedded within the package itself.
FIG. 1
illustrates a cross-section of an integrated circuit package
102
having die side capacitors
106
(“DSC”), land side capacitors
108
(“LSC”), and embedded chip capacitors
110
(“ECC”) in accordance with the prior art. Die side capacitors
106
, as their name implies, are mounted on the same side of the package
102
as the integrated circuit die
104
. In contrast, LSCs
108
are mounted on the opposite side of the package
102
as the die
104
. ECCs
110
are embedded within the package
102
.
Typically, multiple bypassing capacitors are used to provide the desired capacitance.
FIG. 2
illustrates a bottom view of an integrated circuit package
202
having multiple LSCs
204
, which are electrically connected to pads
206
on the bottom of the package
202
in accordance with the prior art. The terminals
208
of each capacitor
204
are connected to a different set of pads
206
. The cross-hatching on terminals
208
is intended to indicate that terminals
208
and pads
206
typically are connected, in an alternating manner, to power and ground planes (not shown) within the package
202
. Analogous figures could be used to illustrate the connection of DSC terminals to package pads, or the connection of ECC terminals to vias within the package.
FIG. 3
illustrates a cross-sectional view of a portion of the integrated circuit package
202
and LSCs
204
of
FIG. 2
along section lines
3
—
3
. When LSCs are multi-layer capacitors, as shown, each capacitor
204
includes multiple planes
302
,
304
of conductive material, separated by layers of dielectric material. Although only six planes are shown, numerous planes are usually present (e.g., hundreds of planes).
Typically, conductive planes
302
,
304
are configured so that alternating planes connect to alternating terminals
306
,
308
around the capacitor. This enables terminals
306
,
308
and planes
302
,
304
to be connected, in an alternating manner, to pads
206
on the package body, as described in conjunction with FIG.
2
. Pads
206
, in turn, connect to either power or ground planes
314
,
316
within the package body through plated or filled vias
318
. Because the capacitors
204
are interconnected through different sets of pads
206
, vias
318
, and power or ground planes
314
,
316
within the package, some “lateral” inductance exists between the capacitors. In other words, the lateral current between capacitors
204
is carried over a conductive loop having a loop area that is bounded by various conductive structures (e.g., pads, vias, and power/ground planes) of the package
202
. According to existing packaging technologies, where the package has one pair of power and ground planes
314
,
316
, the loop area results in about 30 picohenrys (pH)/square of lateral inductance. Where the package has two pairs of power and ground planes
314
,
316
(as illustrated), the total lateral inductance can be reduced to about 15 pH/square.
The capacitors' terminals
306
,
308
are also connected to the integrated circuit load (not shown) through vias
318
, thus enabling the capacitors
204
to provide bypassing capacitance to the integrated circuit. Connection of the capacitors
204
to the load through the vias
318
results in some “vertical” inductance, also referred to as “loop” inductance, to exist in the supply and return via loop between each capacitor
204
and the integrated circuit load.
FIG. 4
illustrates an electrical circuit that simulates the electrical characteristics of the capacitors illustrated in
FIGS. 1-3
. For simplicity, no parasitic resistances of the capacitors are shown in FIG.
4
. The circuit shows a die load
402
, which may require bypassing capacitance in order to function properly. Some of the bypassing capacitance can be supplied by capacitance, modeled by capacitor
404
, located on the die. Other capacitance, however, must be provided off chip, as modeled by off-chip capacitors
406
. The off-chip capacitors
406
could be, for example, the DSCs
106
, LSCs
108
, and/or ECCs
110
illustrated in FIG.
1
.
As described previously, lateral inductance, modeled by inductors
408
, exists between capacitors
406
. In addition, vertical loop inductance, partially modeled by inductor
410
, exists between capacitors
406
and die load
402
. For simplicity, a vertical loop inductance component for each capacitor is not shown.
Because lateral and vertical inductances tend to slow the response time of off-chip capacitors
406
, it is desirable to minimize the magnitudes of these inductances. For LSCs and DSCs, vertical loop inductance can be reduced by using capacitors with interdigital contacts. In addition, vertical loop inductance issues can be addressed by placing off-chip capacitors
406
as electrically close as possible to the die load, such as by using ECCs that may be closer to the load than surface mounted capacitors. Similarly, lateral inductance issues can be addressed by placing adjacent capacitors close to each other. For example, adjacent capacitors may be attached to adjacent pads on the package.
Although these solutions are sufficient in certain cases, as the frequencies and edge rates of electronic devices continue to advance, there is an increasing need for higher levels of bypassing capacitance. In addition, there is a need for capacitance solutions that minimize the lateral inductance present between LSCs, DSCs, and ECCs. Accordingly, there is a need in the art for alternative capacitance solutions in the fabrication and design of electronic assemblies, such as integrated circuit packages.
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Chung Chee-Yee
Li Yuan-Liang
Berhane Adolf D.
Intel Corporation
Schwegman Lundberg Woessner & Kluth P.A.
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