Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2001-06-26
2004-03-30
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S758000, C257S701000, C257S698000, C257S773000
Reexamination Certificate
active
06713860
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to apparatus for providing capacitance to an electronic circuit, and more particularly to providing capacitance to an integrated circuit load, and methods of manufacturing an electronic assembly that includes discrete capacitors electrically connected to a housing.
BACKGROUND OF THE INVENTION
Electronic circuits, and particularly computer and instrumentation circuits, have in recent years become increasingly powerful and fast. As circuit frequencies continue to escalate, with their associated high frequency transients, noise in the power and ground lines increasingly becomes a problem. This noise can arise due to inductive and capacitive parasitics, for example, as is well known. To reduce such noise, capacitors known as bypassing capacitors are often used to provide a stable signal or stable supply of power to the circuitry. Capacitors can also be used to suppress unwanted radiation, to dampen voltage overshoot when an electronic device (e.g., a processor) is powered down, and to dampen voltage droop when the device powers up.
Bypassing capacitors are generally placed as close as practical to a die load or “hot spot” in order to increase the capacitors' effectiveness. Often, the bypassing capacitors are surface mounted to the die side or land side of the package upon which the die is mounted, or embedded within the package itself.
FIG. 1
illustrates a cross-section of an integrated circuit package
102
having die side capacitors
106
(“DSC”) and land side capacitors
108
(“LSC”) in accordance with the prior art. Die side capacitors
106
, as their name implies, are mounted on the same side of the package
102
as the integrated circuit die
104
. In contrast, LSCs
108
are mounted on the opposite side of the package
102
as the die
104
. Embedded chip capacitors (“ECC”) are not illustrated in
FIG. 1
, but would be embedded within the package
102
and electrically connected to package planes and/or pads through conductive vias.
As
FIG. 1
illustrates, the capacitors' terminals are connected to the integrated circuit load through pads, vias
110
, and power or ground planes
112
,
114
within the package, thus enabling the capacitors
106
,
108
to provide bypassing capacitance to the integrated circuit. Connection of the capacitors
106
,
108
to the load through pads, vias
110
, and power or ground planes
112
,
114
results in some “vertical” inductance, also referred to as “loop” inductance, to exist in the supply and return via loop between each capacitor
106
,
108
and the integrated circuit load. According to some existing packaging technologies, the loop area results in about 15-20 picohenrys (pH)/square of vertical inductance. This loop inductance tends to slow the response time of off-chip capacitors.
Typically, multiple bypassing capacitors are used to provide the desired capacitance.
FIG. 2
illustrates a bottom view of an integrated circuit package
202
having multiple LSCs
204
, which are electrically connected to pads
206
on the bottom of the package
202
in accordance with the prior art. The cross-hatching on terminals
208
is intended to indicate that terminals
208
and pads
206
typically are connected, in an alternating manner, to power and ground planes (e.g., planes
112
,
114
,
FIG. 1
) within the package
202
. The electrical connection between the discrete capacitor
204
and the package
202
is accomplished by soldering each terminal
208
of each LSC
204
to a designated pad
206
. Accordingly, where eight-terminal, discrete capacitors are used, as shown in
FIG. 2
, eight electrical connections exist between the capacitor
204
and the package pads
206
. Analogous figures could be used to illustrate the connection of DSC terminals to package pads, or the connection of ECC terminals to vias within the package.
Because the capacitors
204
are interconnected through different sets of pads, vias (e.g., vias
110
, FIG.
1
), and power or ground planes (e.g., planes
112
,
114
,
FIG. 1
) within the package, some “lateral” inductance also exists between the capacitors
204
. In other words, the lateral current between capacitors
204
is carried over a conductive loop having a loop area that is bounded by various conductive structures (e.g., pads, vias, and power/ground planes) of the package
202
. According to some existing packaging technologies, the loop area results in about 15-30 pH/square of lateral inductance, where the amount of vertical inductance is inversely proportional to the number of power and ground planes interconnecting the capacitors. Similar to the effect of vertical inductance, described above, lateral inductance tends to slow the response time of off-chip capacitors.
FIG. 3
illustrates an electrical circuit that simulates the electrical characteristics of the capacitors illustrated in
FIGS. 1-2
. For simplicity, no parasitic resistances of the capacitors are shown in FIG.
3
. The circuit shows a die load
302
, which may require bypassing capacitance in order to function properly. Some of the bypassing capacitance can be supplied by capacitance, modeled by capacitor
304
, located on the die. Other capacitance, however, must be provided off chip, as modeled by off-chip capacitors
306
. The off-chip capacitors
306
could be, for example, DSCs, LSCs, and/or ECCs (e.g., capacitors
106
,
108
, FIG.
1
).
As described previously, lateral inductance, modeled by inductors
308
, exists between capacitors
306
. In addition, vertical inductance, partially modeled by inductor
310
, exists between capacitors
306
and die load
302
. For simplicity, a vertical inductance component for each capacitor is not shown.
Because lateral and vertical inductances tend to slow the response time of off-chip capacitors
306
, it is desirable to minimize the magnitudes of these inductances. For LSCs and DSCs, vertical inductance can be reduced by using capacitors with interdigital contacts. Even with interdigital capacitors, the number of discrete devices that can be mounted to or embedded within a package is limited by the capacitors' dimensions (i.e., the length and width). Thus, the amount of capacitance that can be provided by these off-chip capacitors is also limited by the capacitors' dimensions, among other things.
Besides using interdigital capacitors, vertical inductance issues can be addressed by placing off-chip capacitors
306
as electrically close as possible to the die load, such as by using ECCs, which typically can be placed closer to the load than surface mounted capacitors. Similarly, lateral inductance issues can be addressed by placing adjacent capacitors close to each other. For example, adjacent capacitors are sometimes connected to adjacent pads on the package.
Although these solutions are sufficient in certain cases, as the frequencies and edge rates of electronic devices continue to advance, there is an increasing need for higher levels of bypassing capacitance. In addition, there is a need for capacitance solutions that minimize the vertical and lateral inductances associated with off-chip capacitors. Accordingly, there is a need for alternative capacitance solutions in the fabrication and design of electronic assemblies, such as integrated circuit packages.
REFERENCES:
patent: 4852227 (1989-08-01), Burks
patent: 4883920 (1989-11-01), Tanabe et al.
patent: 5444298 (1995-08-01), Schutz
patent: 5798567 (1998-08-01), Kelly et al.
patent: 5883428 (1999-03-01), Kabumoto et al.
patent: 5973928 (1999-10-01), Blasi et al.
patent: 6272020 (2001-08-01), Tosaki et al.
patent: 6344961 (2002-02-01), Naito et al.
patent: 6388207 (2002-05-01), Figueroa et al.
patent: 10019839 (2001-06-01), None
patent: 0732107 (1996-09-01), None
Intel Corporation
Schwegman Lundberg Woessner & Kluth P.A.
Tran Tan
LandOfFree
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