Electronic arithmetic unit with multiple error detection

Details Electronic arithmetic unit with multiple error detection Electronic arithmetic unit with multiple error detection

1995-02-14

1997-05-13

Gordon, Paul P.

Excavating

371 48, 371 681, G01R 3128, G06F 1100

Patent

active

056299451

ABSTRACT:
An electronic arithmetic unit, such as an ALU, a processor, a controller, or the like, is for the arithmetic gating (combining) of digital operands coded by code bits and supplied via at least one data bus to form data words likewise coded by code bits. The arithmetic gating of the bits of the operands takes place in stages, and in each stage, at least one carry bit is generated. A code-generating unit generates the code bits of the result word from the coded operands while taking into consideration the required operation of the code bits. An additional circuit for duplicated carry generation is assigned to the individual stages. In addition, a testing device is provided for checking the duplicated carry bits for identity. Finally, for each operand, a code checker is provided, which is linked to the individual lines of the at least one data bus via connecting lines, the arithmetic unit and the circuit for duplicated carry generation being connected up between the code checker and the data bus to the connecting lines. In this manner, in addition to faulty operand bits and carry bits, interrupt errors on operand-bit lines can also be detected.

REFERENCES:
patent: 4994993 (1991-02-01), Asghar et al.
patent: 5043990 (1991-08-01), Doi et al.
patent: 5301199 (1994-04-01), Ikenaga et al.
patent: 5450340 (1995-09-01), Nicolaidis
Hayashi et al., A 64b CMOS Mainframe Execution Unit Macrocell with Error Detecting Circuit, Nov. 1991, IECE Transactions, vol. E74, No. 11, pp. 3775-3779.
Fault-Detecting Adder, IBM Technical Disclosure Bulletin, vol. 29, No. 8, Jan. 1987.
R. J. Maier, Low Power Error Correction Architecture for Space, Dec. 1983, IEEE Tranactons on Nuclear Science, vol. NS-30, No. 6, pp. 4333-4338.
Nicolaidis, "Efficient Implementations of Self-Checking Addersard ALUs," 23rd IEEE International Symposium on Fault Tolerant Computing Jun. 1993, pp. 586-595.
I.G. Maloff, "Checking Codes for Digital Computers," Proceedings of the IRE, Apr. 1955, pp. 487-488.
D.T. Brown, "Error Detecting and Correcting Binary Codes for Arithmetic Operands," IRE Transactions Electronic Computers, Sep. 1960, pp. 333-337.
W.W. Peterson, "On Checking and Adder," IBM Journal, Apr. 1958, pp. 166-168.
J.C. Lo et al., "An SFS Berger Check Prediction ALU and its Application to Self-Checking Processor Designs," IEEE Transactions on Computer-Aided Design, vol. II, No. 4, Apr. 1992, pp. 525-540.
H.P. Holzpfel, "Fault-Tolerant VLS Processor," 3rd International GI/ITG/GMA Conference, Sep. 1987, pp. 72-82.
B. Khodadad-Mostashiry, "Parity Prediction In Combinational Circuits," Proceedings of the FTCS-9, IEEE Computer Society, 1979, pp. 185-188.
E. Fujiawara et al., "Fault-Tolerant Arithmetic Logic Unit Using Parity-Based Codes," The Transactions of IEEE of Japan, vol. E64, No. 10, Oct. 1981, pp. 653-660.
J. Wakerly, "Error Detecting Codes, Self-Checking Circuits and Applications," The Computer Science Library, 1978, pp. 66-67.

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