Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Non-single crystal – or recrystallized – material with...
Reexamination Certificate
2000-05-16
2003-04-08
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Non-single crystal, or recrystallized, material with...
C257S066000, C257S072000, C257S075000
Reexamination Certificate
active
06545294
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed to a polycrystalline semiconductor thin film layer and the method of production thereof, to a semiconductor device and the method of production thereof, and to an electronic apparatus, more specifically to an effective technology suitable for application in manufacturing transistors on the surface of polycrystalline semiconductor thin film layer (thin film transistors, TFT), polycrystalline layer for producing the thin film transistors, and electronic devices such as liquid crystal display devices or information processing devices incorporating the thin film transistors.
2. Description of the Related Art Including Information Disclosed Under 37 CFR 1.97 and 37 CFR 1.98
Thin film transistors (TFT) used heretofore in the conventional image display devices and the like have been formed on a substrate material such as amorphous silicon or micro-crystalline silicon made by means of plasma CVD on an insulating substrate of glass or quartz, with the polycrystalline silicon as element material made by means of melt and recrystallization method such as excimer laser annealing.
TFT made of polycrystalline silicon as material has field effect mobility of 100 to 200 cm2/Vsec due to decreased mobility caused by the carrier scattering in the grain boundary, in comparison with the field effect mobility ideal in the single-crystalline silicon (Japanese Unexamined Patent Publication No. H9-27452). The mobility is approximately 500 cm2/Vsec in single-crystalline silicon MOS-FET (S. M. Sze, Physics of Semiconductor Devices, Second Edition, Wiley, P449).
The position and the number of crystal grains formed on the channel of a transistor is not controllable and hence the device performance is not uniform compared to the single-crystalline silicon MOS-FET (Japanese Unexamined Patent Publication No. H10-291897).
Numerous techniques have been devised and proposed for enlarging the size of grains and for controlling the position of them. These techniques include, among others, a method for solid-state crystallization of amorphous silicon using the islet-patterned nuclei formed on the insulating substrate (Japanese Unexamined Patent Publication No. H8-316485), a method for forming a deposited amorphous layer on a polycrystalline silicon and making use of polycrystalline silicon exposed on the surface as the nuclei for next solid phase crystallization (Japanese Unexamined Patent Publication No. H8-31749), a method for selectively producing amorphous layers from partially crystallized silicon thin film by using ion-implantation and making use of the residual crystallization as nuclei for recrystallization (Japanese Unexamined Patent Publication No. H10-55960), a method for accelerating the rate of crystallization by diffusion of metal elements (Japanese Unexamined Patent Publication No. H9-27452), and a method for gradually altering the irradiating energy and irradiation period of time of pulse laser annealing (Japanese Unexamined Patent Publication No. H10-97993).
BRIEF SUMMARY AND OBJECTS OF THE INVENTION
The methods as cited above of crystallization are considered not to be sufficiently maturated, resulting in the maximum grain size attainable of approximately 2 microns, with insufficient positional control of crystal grains. This is far from the practical usable size of thin film transistors, approximately 8 microns, required for the large size liquid crystal display panels, and the uniformity of device performance is not well achieved.
In addition, the crystal orientation of polycrystalline thus formed is disordered, so that there arises a problem of dispersion of device performance of field effect mobility depending on the crystal orientation.
The technologies cited above have not been successful to replace therewith the thin film transistor devices of low performance using the conventional amorphous silicon.
Thus, in order to achieve an image display device of larger size with higher performance and the like, there is a need to provide a technology for growing polycrystalline silicon for the element material of thin film transistors with a crystal orientation aligned to a specific direction (grain size larger than approximately 8 microns), and for finely controlling the position of crystal grains.
Therefore the present invention has been made in view of the above circumstances and has an object to overcome the above problems and to provide, in a semiconductor device formed by a plurality of thin film transistors on a polycrystalline layer, a manufacturing technology of the semiconductor device allowing the dispersion of characteristics such as field effect mobility of each of the thin film transistors and the like to be minimized.
Another object of the present invention is to provide a method for forming thin film transistors in a single crystal grain region by enlarging the size of crystal grains served for polycrystalline layer.
Still another object of the present invention is to provide a method for aligning the crystal orientation of crystal grains served for the polycrystalline layer.
Yet another object of the present invention is to provide a method for identifying the position of crystal grains served for a polycrystalline layer at higher precision.
Still another object of the present invention is to provide a polycrystalline layer of larger crystal grains in which the crystal orientation of crystal grains may be aligned and the position of crystal grains is identified at higher precision and transistors may be formed within a single crystal grain region, and a method for producing thereof.
Additional objects and advantages of the invention will be according to part in the description which follows and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
In brief, the overview of the principal of the present invention disclosed in this application may be as follows:
(1) An electronic apparatus comprising,
An insulating substrate (such as a glass substrate) and polycrystalline layer (polycrystalline silicon thin film) of n layers (where n≧2), sequentially laminated on the insulating substrate with crystal grains (silicon crystal grains) sparse on the surface of thin film, the number of the crystal grains at each of the layers in a given planar area being reduced from lower to upper layer. In other words the size of the crystal grains is enlarging from lower to upper layer, the interval of crystal grains also is enlarging from lower to upper layer. On the surface area of each of the polycrystalline layers from first to (n−1)th layer, projections each formed by a single crystal may be formed at a given interval, the crystal having a tip in a specific crystal orientation, the crystal grain served for the nth polycrystalline layer being a single crystal formed on the projections of the (n−1)th polycrystalline layer next thereto, and respective of projections of each layer is positioned beneath the projection of the (n−1)th polycrystalline layer. The interval of the projections is enlarging from lower to upper layer. The interval of the projections becomes twice for each lamination. The thickness of the polycrystalline layer is twice of the thickness of the lower next layer to the polycrystalline layer.
A polycrystalline layer as have been described above may be produced by (a) forming on an insulating substrate (glass substrate) an amorphous layer (amorphous silicon layer) to crystallize so as to sparse crystal grains (silicon crystal grains) on the film layer surface to provide a polycrystalline layer (polycrystalline silicon layer); (b) anisotropically etching up to a predetermined depth the polycrystalline layer so as to obtain a specific crystal orientation and to selectively maintain the area of given interval; (c) anisotropically etching the entire surface of the polycrys
Miyao Masanobu
Nakagawa Kiyokazu
Sugii Nobuyuki
Yamaguchi Shin'ya
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
Tran Minh Loan
LandOfFree
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