Electron exposure apparatus

Details Electron exposure apparatus Electron exposure apparatus

1998-06-05

2002-04-02

Adams, Russell (Department: 2851)

Photocopying

Projection printing and copying cameras

Illumination systems or details

C355S071000, C430S296000

Reexamination Certificate

active

06366340

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electron exposure apparatus employed in a micro-fabrication technique using a scanning probe microscope.
2. Description of the Related Art
A nanometer-scale-fabrication technique is indispensable for fabricating higher integrated electronic device and higher densificated recording media. However, the minimum feature size of the electronic device is limited to about 100 nm by the wavelength of a light source and a lens material used in optical lithography. Further, the resolution margin in a master plate of a recording medium is expected to be smaller in the near future. A nanometer-scale-fabrication technique using a scanning probe microscope, such as described in, S. C. Minne et al., “Fabrication of 0.1 &mgr;m Metal Oxide Semiconductor Field-Effect Transistor” Appl. Phys. Lett. 66(6) 6 Feb. 6, 1995 pp. 703-705, or Hyongsok T. Soh et al., “Fabrication of 100 nm pMOSFETs with Hybrid AFM/STM Lithography” (1997 SYMPOSIUM ON VLSI TECHNOLOGY), is promising for fabricating nanometer-scale devices and recording media. In general, this method is performed by applying a voltage between tip and wafer, and the resolution is atomic level in principle.
Further, a lithography system having a plurality of cantilevers has been also proposed as disclosed in U.S. Pat. No. 5,666,190.
SUMMARY OF THE INVENTION
In the case of using the scanning probe microscope as an electron exposure apparatus, high speed scanning under the simultaneous use of a plurality of tips is effective as in a micro-fabricated device with integrated electrostatic actuators, which has been proposed in U.S. Pat. No. 5,666,190 or the parent application of the present application. On the one hand, however, this method needs to control two, i.e., exposure doses and wafer-to-tip distances with respect to respective tips. This method also requires not only their drivers but also a control system for generally controlling all of them, thereby leading to a complex apparatus.
The present invention has taken note of the fact that the Coulomb forces, which are generated by the exposure current, are large enough to bend the cantilevers and to allow the respective tips to contact the wafer surface. Namely, the distance between the tip group and wafer surface is roughly controlled at the start of the electron exposure. In this case, each side of the tip group may be set to have a suitable wafer-to-tip distance. If done in this way, then all the tips can have suitable wafer-to-tip distances within a range of a given dispersion incident to the fabrication of the tip group. After the electron exposure has been started, the wafer-to-tip distances at each side of the tip group are monitored and controlled to keep the distance determined at the start of the electron exposure.
In other words, in the present invention, electron exposure is carried out while each side of a tip group maintains a suitable wafer-to-tip distance determined at the start of the electron exposure. In doing so, individual tips automatically bend along the surface of the wafer, even if the surface has micro-roughness, by the Coulomb force supplied from exposure current. Thus, wafer-to-tip distance control is not required on each individual tip during electron exposure. Of course, the exposure-current control is required for each individual tip.
Typical ones of various embodiments of the present invention have been shown in brief. However, the various inventions of the present application and specific configurations of these inventions will be understood from the following description.


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Applied Physics Letters, vol. 66, No. 6, Feb. 6, 1995, “Fabrication of 0.1&mgr;m metal oxide semiconductor field-effect transistors with the atomic force microscope”, S. C. Minne et al, pp. 703-705.
1997 Symposium on VLSI Technology, “Fabrication on 100nm pMOSFETs with Hybrid AFM/STM Lithography”, Soh et al.

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