Electric lamp and discharge devices – With luminescent solid or liquid material – Vacuum-type tube
Reexamination Certificate
2000-05-11
2003-04-08
Patel, Ashok (Department: 2879)
Electric lamp and discharge devices
With luminescent solid or liquid material
Vacuum-type tube
C313S495000, C313S309000, C313S336000, C313S351000
Reexamination Certificate
active
06545407
ABSTRACT:
BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates to field emission devices. More particularly, the present invention relates to a field emission device having a gate electrode including a layer of nanocrystalline or microcrystalline silicon that provides improved adhesion with an underlying silicon dioxide layer. The invention is also directed to methods of making and using the field emission device.
2. The Relevant Technology
Integrated circuits and related structures are currently manufactured by an elaborate process in which semiconductor devices, insulating films, and patterned conducting films are sequentially constructed in a predetermined arrangement on a semiconductor substrate. In the context of this document, the term “semiconductor substrate” is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term “substrate” refers to any supporting structure including but not limited to the semiconductor substrates described above. The term semiconductor substrate is contemplated to include such structures as silicon-on-insulator and silicon-on-sapphire.
Computer monitors, televisions, and other visual display devices have traditionally used cathode ray tubes which use an electron gun to direct a scanning electron beam upon a phospholuminescent screen. With the advent of portable personal computers, telecommunication devices, and other such appliances, there has been an increased interest in high quality lightweight display panels that are not as bulky as cathode ray tubes. A promising and useful development has been the incorporation of field emission devices into integrated circuits, semiconductor structures or related products to produce flat panel displays.
A field emission device typically includes an electron emission structure or tip configured for emitting a flux of electrons upon application of an electric field thereto. The emitted electrons may be directed to a transparent panel having phospholuminescent material placed thereon. By selecting and controlling the operation of an array of miniaturized field emission devices, a selected visual display that is suitable for use in computer and other visual and graphical applications may be produced. Flat panel displays using field emission devices typically have a greatly reduced thickness compared to cathode ray tubes. As a result, field emission devices have been shown to be an attractive alternative to cathode ray tube display devices.
Field emission devices used in flat panel displays are generally multilayer structures formed over a semiconductor, glass, or other substrate.
FIG. 1
illustrates an example of a field emission device in an intermediate step during the manufacturing process. Multilayer structure
10
comprises two structures that will be used as electrodes during operation of the completed field emission device. In particular, cathode structure
12
and low potential gate electrode structure
14
will be used to establish an electric field across electron emission structure
16
. The two electrodes are separated by a dielectric layer
18
.
In order to freely emit a flow of electrons, electron emission structure
16
must be exposed during manufacturing by removing material positioned thereon. One of the steps of exposing electron emission structure
16
may include conducting a planarization operation on multilayer structure
10
, including a layer
21
, by chemical-mechanical planarization or other mechanical or non-mechanical means, thereby producing a substantially planar surface indicated by the dashed line at
20
. Layer
21
comprises a conductive material such as chromium, aluminum, alloys thereof, and/or silicon.
When chemical-mechanical planarization is used to expose electron emission structure
16
, there is the risk of delamination of layer
21
from dielectric layer
18
if the bonding forces therebetween are not sufficiently strong. Typically, it has been understood that the bonding forces between a silicon dioxide substrate and an overlying silicon layer are related to the internal compressive stress of the overlying silicon layer. Generally, higher compressive stress values tend to correlate with poor bonding and increased risk of delamination. While not a fixed rule, it has been observed in the past that compressive stress less than 2×10
9
dynes/cm
2
are preferred in some circumstances in order to reduce the tendency of the layers to delaminate.
Nonetheless, an amorphous silicon layer deposited on a silicon dioxide layer using plasma-enhanced chemical vapor deposition (PECVD) frequently delaminates during a subsequent chemical-mechanical planarization operation, even though the compressive stress of the amorphous silicon layer may be relatively low. The difficulties involved in forming an adequate bond between an amorphous silicon layer deposited using PECVD and a silicon dioxide substrate have generally discouraged the use of PECVD amorphous silicon layers when chemical-mechanical planarization steps are to be conducted thereon. As a result, when chemical-mechanical planarization has been used in the prior art, layer
21
has generally consisted of materials other than amorphous silicon.
However, in general, amorphous silicon is understood to be a preferred material in forming other portions of field emission devices and other semiconductor structures. Moreover, PECVD is a preferred and efficient method for depositing silicon layers over a substrate. The inability to use PECVD amorphous silicon layers as described above when chemical-mechanical planarization operations are subsequently conducted has been a persistent problem that, if overcome, would significantly improve the cost-effectiveness and reliability of the process of manufacturing field emission devices.
In view of the foregoing, it is clear that there is a need for methods of manufacturing field emission devices in which a silicon layer may be deposited by PECVD on a dielectric layer without delaminating during subsequent chemical-mechanical planarization. In particular, it would be an advancement in the art to provide a method for depositing silicon on silicon dioxide to produce a bond sufficiently strong to resist subsequent delamination in the fabrication of a field emission device.
SUMMARY OF THE INVENTION
The present invention relates to a field emission device having a gate electrode structure that includes a silicon adhesion layer of nanocrystalline or microcrystalline silicon which provides improved adhesion with an underlying layer of silicon dioxide. The invention also includes methods of making and using the field emission device. According to the invention, mechanical planarization may be conducted during the manufacturing process without causing the gate electrode structure to delaminate.
The method of the invention includes forming one or more electron emission structures over a cathode structure and a substrate. A silicon dioxide dielectric layer is conformally deposited over the electron emission structures. A silicon adhesion layer is then formed on the silicon dioxide dielectric layer by plasma-enhanced chemical vapor deposition in an atmosphere of silane and hydrogen at a ratio in a range from about 1:15 to about 1:40. The silicon of the silicon adhesion layer has a nanocrystalline or microcrystalline structure in which the mean grain size is in a range from about 200 Å to about 1,000 Å. Preferably, the silicon of the silicon adhesion layer is undoped or is doped at a dopant concentration not in excess of about 10
21
atoms/cm
3
. A layer of amorphous silicon, which may be phosphorous-doped, is preferably next deposited on the silicon adhesion layer.
Chemical-mechanical planarization or another mechanical or non-mechanical planarization operation is then conducted to form a substan
Micro)n Technology, Inc.
Patel Ashok
Workman & Nydegger & Seeley
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