Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2002-08-23
2004-11-09
Tang, Minh N. (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S754120
Reexamination Certificate
active
06815960
ABSTRACT:
Japanese Patent Application No. 2001-255993 filed on Aug. 27, 2001, and Japanese Patent Application No. 2001-342201 filed on Nov. 07, 2001, are hereby incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
The present invention relates to an electron beam test system and an electron beam test method, and particularly relates to an electron beam test system and an electron beam test method can judge high/low potentials with respect to a DC signal and a signal having no change in potential from the previous time of timing to be observed.
FIG. 4
is a constructional view showing a conventional electron beam test system.
The electron beam test system
100
has an electron beam prober
101
, a high accuracy LSI tester
102
for operating a device connected to this electron beam prober
101
, a control EWS (engineering work station)
106
for controlling operations of the electron beam prober
101
and the high accuracy LSI tester
102
.
The electron beam prober
101
has a structure constructed such that a beam blanker
103
for forming a pulse beam, an analytical grid
104
for observing a potential distribution and measuring a waveform, and a waveform measuring unit
105
connected to this analytical grid
104
are added to a SEM (scanning electron microscopy). A fixing stage
109
for placing a semiconductor wafer is arranged on an X-Y moving stage
108
.
A non-defective or defective semiconductor wafer (semiconductor integrated circuit device) is placed on the fixing stage
109
.
This semiconductor wafer is connected to a test head
110
, and is operated by this test head
110
. In other words, a predetermined test pattern signal including a clock signal is inputted from the test head
110
to each input terminal of the semiconductor wafer.
An electron beam is irradiated by a field emission gun (FE-Gun)
107
to the operated semiconductor wafer through the beam blanker
103
.
A secondary electron from the semiconductor wafer is detected by a secondary electron detector
111
through the analytical grid
104
, and a voltage waveform of the operated semiconductor wafer, etc. are measured by the waveform measuring unit
105
.
FIG. 5
shows one example of the test pattern signal supplied to the semiconductor wafer and its measured waveform. Here, one example of a clock signal waveform of wiring of the semiconductor wafer and a differential waveform appearing on a passivation film is shown.
As shown in this figure, the differential waveform appearing on the passivation film is detected in the voltage waveform measurement in the electron beam test system. In timing in which the test pattern signal supplied to the semiconductor wafer becomes a pattern signal to be observed, a clock period is lengthened and a potential contract image at an arbitrary time is taken in.
In the above conventional electron beam test system, the image of a low potential becomes light and the image of a high potential becomes dark in a pulse signal such as a clock signal. Accordingly, the observation can be made similarly to a state having no passivation film even when no passivation film is separated.
However, in the conventional technique, the image becomes gray (intermediate color) with respect to the DC (direct current) signal and a signal having no change in potential from the previous time of timing to be observed. Therefore, no high/low potentials can be judged so that it is difficult to recognize the potential.
Further, in the conventional technique, the processing of taking in the potential contrast is performed every time the predetermined desirable test pattern signal is inputted while the test pattern is looped. Accordingly, it is necessary to set plural shots in which the potential contrast is taken in every time the test pattern is looped. The obtained plural potential contrasts were integrated, and the final potential contrast image was generated.
Accordingly, in the conventional technique, it takes time to generate the image of the potential contrast. As a result, a problem exists in that faulty or breakdown caused by process results cannot be rapidly analyzed.
In addition, in such a conventional technique, a problem exists in that no defective phenomenon having no repeating reproducibility can be observed.
BRIEF SUMMARY OF THE INVENTION
In consideration of the above problems, the present invention may provide an electron beam test system and an electron beam test method capable of obtaining potential information of the semiconductor integrated circuit device by observing one phenomenon, and judge high/low potentials with respect to the DC signal and a signal having no change in potential from the previous time of timing to be observed.
(1) One aspect of the present invention relates to an electron beam test system which obtains a potential contrast for analysis by irradiating an electron beam to a semiconductor integrated circuit device to be analyzed.
This electron beam test system comprises:
a tester which supplies a test pattern signal for analysis to the semiconductor integrated circuit device to be analyzed, and holds the test pattern signal at a given timing, and then changes a potential of a direct current power source of the semiconductor integrated circuit device to be analyzed and a potential of the held test pattern signal to a reference potential; and
a detector which takes in the potential contrast right after the reference potential is set.
This electron beam system adopts a construction in which the test pattern signal in timing to be observed is held for a predetermined time, and this held test pattern signal (input signal) and the direct current power source potential are changed to the reference potential. When the held test pattern signal, etc. are changed to the reference potential, the signal to be observed can be detected as a differential waveform by adopting this construction even when this signal to be observed is a DC (direct current) signal and a signal having no change in potential from the previous time of timing to be observed.
As mentioned above, a high or low potential can be also judged with respect to the DC signal and the signal having no change in potential from the previous time of the timing to be observed.
In addition, in accordance with the present invention, a potential of a signal line can be detected as an attenuation signal on a passivation film. Therefore, the generation of a preferable potential contrast image can be realized by the observation of one phenomenon (the observation of a single shot phenomenon) without looping the test pattern signal. Namely, the potential contrast image can be generated by observing the single shot operating phenomenon of the attenuation of a waveform. Therefore, it is possible to realize a system capable of simply obtaining potential information in the single shot observed from above the passivation film of the semiconductor integrated circuit device.
(2) This electron beam system may further include:
an electron gun which irradiates the electron beam to the semiconductor integrated circuit device to be analyzed; and
an analytical grid for observing a potential distribution, which is arranged between the electron gun and the semiconductor integrated circuit device to be analyzed.
(3) This electron beam system may further include a stage for placing the semiconductor integrated circuit device to be analyzed, and freely and horizontally movable.
(4) Another aspect of in the present invention relates to an electron beam test system which obtains a potential contrast for analysis by irradiating an electron beam to a semiconductor integrated circuit device to be analyzed.
This electron beam test system comprises:
a first stage for placing the semiconductor integrated circuit device to be analyzed;
a second stage for placing a non-defective semiconductor integrated circuit device for comparison with the semiconductor integrated circuit device to be analyzed;
a tester which supplies a test pattern signal for analysis to each of the semiconductor integrated circuit device to be analyzed and the non-defect
LandOfFree
Electron beam test system and electron beam test method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Electron beam test system and electron beam test method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electron beam test system and electron beam test method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3284988